XC3S200A-4VQG100C Datasheet, PDF (70/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
VQ100: 100-lead Very Thin Quad Flat Package
The XC3S50A and XC3S200 are available in the 100-lead
very thin quad flat package, VQ100.
Table 63 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
The VQ100 does not support Suspend mode (SUSPEND
and AWAKE are not connected), the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode,
or daisy chain configuration (DOUT is not connected).
Table 63 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the
XC3S200A, highlighted in light blue. See "Footprint
Migration Differences," page 72 for additional information.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 63: Spartan-3A VQ100 Pinout
Bank
Pin Name
Pin
0
IO_0/GCLK11
P90
0
IO_L01N_0
P78
0
IO_L01P_0/VREF_0
P77
0
IO_L02N_0/GCLK5
P84
0
IO_L02P_0/GCLK4
P83
0
IO_L03N_0/GCLK7
P86
0
IO_L03P_0/GCLK6
P85
0
IO_L04N_0/GCLK9
P89
0
IO_L04P_0/GCLK8
P88
0
IO_L05N_0
P94
0
IO_L05P_0
P93
0
IO_L06N_0/PUDC_B
P99
0
IO_L06P_0/VREF_0
P98
0
IP_0
P97
0
IP_0/VREF_0
P82
0
VCCO_0
P79
0
VCCO_0
P96
1
IO_L01N_1
P57
1
IO_L01P_1
P56
1
IO_L02N_1/RHCLK1
P60
Type
CLK
IO
VREF
CLK
CLK
CLK
CLK
CLK
CLK
IO
IO
DUAL
VREF
IP
VREF
VCCO
VCCO
IO
IO
CLK
Table 63: Spartan-3A VQ100 Pinout(Continued)
1
IO_L02P_1/RHCLK0
P59
CLK
1
IO_L03N_1/TRDY1/RHCLK3 P62
CLK
1
IO_L03P_1/RHCLK2
P61
CLK
1
IO_L04N_1/RHCLK7
P65
CLK
1
IO_L04P_1/IRDY1/RHCLK6
P64
CLK
1
IO_L05N_1
P71
IO
1
IO_L05P_1
P70
IO
1
IO_L06N_1
P73
IO
1
IO_L06P_1
P72
IO
1
IP_1/VREF_1
P68
VREF
1
VCCO_1
P67
VCCO
2
IO_2/MOSI/CSI_B
P46
DUAL
2
IO_L01N_2/M0
P25
DUAL
2
IO_L01P_2/M1
P23
DUAL
2
IO_L02N_2/CSO_B
P27
DUAL
2
IO_L02P_2/M2
P24
DUAL
2
IO_L03N_2/VS1 (3S50A)
IO_L04P_2/VS1 (3S200A)
P30
DUAL
2
IO_L03P_2/RDWR_B
P28
DUAL
2
IO_L04N_2/VS0
P31
DUAL
2
IO_L04P_2/VS2 (3S50A)
IO_L03N_2/VS2 (3S200A)
P29
DUAL
2
IO_L05N_2/D7 (3S50A)
IO_L06P_2/D7 (3S200A)
P34
DUAL
2
IO_L05P_2
P32
IO
2
IO_L06N_2/D6
P35
DUAL
2
IO_L06P_2 (3S50A)
IO_L05N_2 (3S200A)
P33
IO
2
IO_L07N_2/D4
P37
DUAL
2
IO_L07P_2/D5
P36
DUAL
2
IO_L08N_2/GCLK15
P41
CLK
2
IO_L08P_2/GCLK14
P40
CLK
2
IO_L09N_2/GCLK1
P44
CLK
2
IO_L09P_2/GCLK0
P43
CLK
2
IO_L10N_2/D3
P49
DUAL
2
IO_L10P_2/INIT_B
P48
DUAL
IO_L11N_2/D0/DIN/MISO
2
(3S50A)
IO_L12P_2/D0/DIN/MISO
(3S200A)
P51
DUAL
2
IO_L11P_2/D2
P50
DUAL
2
IO_L12N_2/CCLK
P53
DUAL
70
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DS529-4 (v2.0) August 19, 2010