XC3S200A-4VQG100C Datasheet, PDF (41/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (V_CCAUX=3.3V)(Continued)
Package Type
FT256, FG320,
FG400, FG484,
VQ100, TQ144
FG676
Signal Standard
(IOSTANDARD)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
–
22
–
LVDS_33
8
–
27
–
BLVDS_25
1
1
4
4
MINI_LVDS_25
8
–
22
–
MINI_LVDS_33
8
–
27
–
LVPECL_25
Input Only
LVPECL_33
Input Only
RSDS_25
8
–
22
–
RSDS_33
8
–
27
–
TMDS_33
8
–
27
–
PPDS_25
8
–
22
–
PPDS_33
8
–
27
–
DIFF_HSTL_I
–
5
–
10
DIFF_HSTL_III
–
3
–
4
DIFF_HSTL_I_18
6
6
8
8
DIFF_HSTL_II_18
–
2
–
2
DIFF_HSTL_III_18
4
4
5
4
DIFF_SSTL18_I
3
6
3
7
DIFF_SSTL18_II
–
4
–
4
DIFF_SSTL2_I
5
5
9
9
DIFF_SSTL2_II
–
3
–
4
DIFF_SSTL3_I
3
4
4
5
DIFF_SSTL3_II
2
3
3
3
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2. The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the V_IL/V_IH voltage
limits for the respective I/O standard.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
41