XC3S200A-4VQG100C Datasheet, PDF (128/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
User I/Os by Bank
Table 88 indicates how the 502 available user-I/O pins are
distributed between the four I/O banks on the FG676
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 88: User I/Os Per Bank for the XC3S1400A in the FG676 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
120
82
20
1
9
Right
1
130
67
15
30
10
Bottom
2
120
67
14
21
10
Left
3
132
97
18
0
9
TOTAL
502
313
67
52
38
CLK
8
8
8
8
32
Footprint Migration Differences
The XC3S1400A FPGA is the only Spartan-3A device
offered in the FG676 package. However, Table 89
summarizes footprint and functionality differences between
the XC3S1400A and the XC3SD1800A in the Spartan-3A
DSP family. There are 17 unconnected balls in the
XC3S1400A that become 16 input-only pins and one I/O pin
in the XC3SD1800A. All other pins not listed in Table 89
unconditionally migrate between the Spartan-3A devices
and the Spartan-3A DSP devices available in the FG676
package. The arrows indicate the direction for easy
migration. For more details on the Spartan-3A DSP family
and pinouts, and additional differences in the FG676 pinout
for the XC3SD3400A device, see DS610.
Table 89: FG676 Footprint Differences
Pin
A24
B24
D5
E6
E9
F9
F18
G18
W18
Y8
Y18
Y19
AA8
AC5
AC22
AD5
AD23
Bank
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
XC3S1400A
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Migration
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
XC3SD1800A
INPUT
INPUT
INPUT
VREF (INPUT)
INPUT
VREF (INPUT)
INPUT
VREF (INPUT)
VREF (INPUT)
VREF (INPUT)
INPUT
INPUT
INPUT
INPUT
I/O
INPUT
VREF(INPUT)
DIFFERENCES
17
Legend:
Æ
This pin can unconditionally migrate from the device on
the left to the device on the right. Migration in the other
direction is possible depending on how the pin is
configured for the device on the right.
128
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DS529-4 (v2.0) August 19, 2010