XC3S200A-4VQG100C Datasheet, PDF (23/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Min
Min
Setup Times
T_PSDCM
When writing to the Input
LVCMOS25⁽²⁾,
XC3S50A
2.45
2.68
Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0,
setup of data at the Input pin to with DCM⁽⁴⁾
XC3S200A
2.59
2.84
the active transition at a Global
Clock pin. The DCM is in use. No
XC3S400A
2.38
2.68
Input Delay is programmed.
XC3S700A
2.38
2.57
XC3S1400A
1.91
2.17
T_PSFD
When writing to IFF, the time from LVCMOS25⁽²⁾,
XC3S50A
2.55
2.76
the setup of data at the Input pin IFD_DELAY_VALUE = 5,
to an active transition at the
without DCM
XC3S200A
2.32
2.76
Global Clock pin. The DCM is not
in use. The Input Delay is
XC3S400A
2.21
2.60
programmed.
XC3S700A
2.28
2.63
XC3S1400A
2.33
2.41
Hold Times
T_PHDCM
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
XC3S50A
XC3S200A
XC3S400A
XC3S700A
-0.36
-0.52
-0.33
-0.17
-0.36
-0.52
-0.29
-0.12
T_PHFD
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 5,
without DCM
XC3S1400A
XC3S50A
XC3S200A
XC3S400A
XC3S700A
-0.07
-0.63
-0.56
-0.42
-0.80
0.00
-0.58
-0.56
-0.42
-0.75
XC3S1400A -0.69
-0.69
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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