XC3S200A-4VQG100C Datasheet, PDF (107/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

FG400 Footprint
Left Half of FG400
Package (Top View)
I/O: Unrestricted,
155 ^{general-purpose user I/O}
INPUT: Unrestricted,
46 ^{general-purpose input pin}
51
DUAL: Configuration pins,
then possible user I/O
VREF: User I/O or input
26 ^{voltage reference for bank}
CLK: User I/O, input, or
32 ^{clock buffer input}
2
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
4 ^{port pins}
SUSPEND: Dedicated
2
SUSPEND and
dual-purpose AWAKE
Power Management pins
GND: Ground
43
VCCO: Output voltage
22 ^{supply for bank}
VCCINT: Internal core
9 ^{supply voltage (+1.2V)}
VCCAUX: Auxiliary supply
8 ^voltage
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Bank 0
1
2
3
4
5
6
7
8
9
10
A
GND
I/O
L32P_0
VREF_0
I/O
L30P_0
I/O
L29P_0
I/O
L26P_0
I/O
L25P_0
I/O
L24N_0
I/O
I/O
L18N_0 L18P_0
GCLK11 GCLK10
I/O
L16P_0
GCLK6
B
I/O
L02P_3
I/O
L32N_0
PUDC_B
I/O
L30N_0
VCCO_0
I/O
L26N_0
GND
I/O
I/O
I/O _{VCCO_0}
L24P_0 L20P_0 L19P_0
C
I/O
L03P_3
I/O
L02N_3
GND
I/O
L29N_0
I/O
L28P_0
I/O
L25N_0
I/O
L21P_0
I/O
L20N_0
I/O
L19N_0
I/O
L16N_0
GCLK7
D
I/O
L05P_3
I/O
L03N_3
I/O
L01N_3
I/O
L01P_3
I/O _{VCCO_0} I/O
L28N_0
L21N_0
GND
I/O
L17P_0
GCLK8
E
I/O
L05N_3
VCCO_3
I/O
L10P_3
TMS
GND
I/O
L31P_0
I/O
L27P_0
I/O
L23P_0
I/O
L22P_0
I/O
L17N_0
GCLK9
F
I/O
L13P_3
I/O
L10N_3
I/O
L09P_3
I/O
L06P_3
TDI
I/O
L31N_0
I/O
L27N_0
I/O
L23N_0
I/O
L22N_0 VCCO_0
VREF_0
I/O
G L13N_3
VREF_3
GND
I/O
L12P_3
I/O
L09N_3
I/O
L06N_3
INPUT _INPUT
L04N_3
VREF_3
L04P_3
INPUT
INPUT
INPUT
H
VCCAUX
I/O
L12N_3
I/O
L14N_3
I/O
L08N_3
VCCO_3
I/O
L08P_3
INPUT
GND
INPUT INPUT
J
I/O
L17P_3
LHCLK0
I/O
L16N_3
I/O
L16P_3
I/O
L14P_3
I/O
L07N_3
I/O
L07P_3
INPUT _INPUT
L11N_3
VREF_3
L11P_3
GND VCCINT
K
GND
I/O
L17N_3
LHCLK1
I/O
L18P_3
LHCLK2
I/O
L20P_3
LHCLK4
INPUT
L19N_3
INPUT
L19P_3
INPUT
L15N_3
INPUT _VCCINT
L15P_3
GND
I/O
I/O
L
L21P_3
TRDY2
VCCO_3
L18N_3
IRDY2
LHCLK6
LHCLK3
GND
I/O
L20N_3
LHCLK5
INPUT
L23N_3
INPUT _VCCAUX
L23P_3
GND VCCINT
I/O
I/O
M L21N_3 L22P_3
LHCLK7 VREF_3
I/O
L22N_3
I/O
L24P_3
I/O
L24N_3
INPUT
L31P_3
INPUT
L27N_3
INPUT _VCCINT
L27P_3
GND
N
I/O
L25P_3
I/O
L25N_3
I/O
L26P_3
I/O _{VCCO_3} INPUT
L26N_3
L35N_3
INPUT
L31N_3
GND
INPUT _VCCINT
VREF_2
P
I/O
L28P_3
GND
I/O
L29P_3
I/O
L29N_3
INPUT
L35P_3
INPUT
L39P_3
INPUT
L39N_3
VREF_3
INPUT
VREF_2
INPUT
INPUT
VREF_2
R
I/O
L28N_3
I/O
L30P_3
I/O
L30N_3
I/O
L33N_3
I/O
L36P_3
GND
I/O _INPUT
L04N_2
GND
INPUT
T
I/O
L32P_3
VREF_3
I/O
L32N_3
I/O
L33P_3
I/O _VCCAUX I/O
L36N_3
L04P_2
I/O
I/O
I/O
L06P_2
L07P_2
RDWR_B
L11P_2
I/O
L14N_2
D4
U
I/O _{VCCO_3} I/O
L34P_3
L34N_3
I/O
L01P_2
M1
I/O
L05N_2
I/O
L06N_2
I/O
L07N_2
VS2
VCCO_2
I/O
L11N_2
I/O
L14P_2
D5
V
I/O
L37P_3
I/O
L37N_3
GND
I/O
L01N_2
M0
I/O
L05P_2
I/O
L09P_2
VS1
I/O
L12P_2
D7
I/O
L13P_2
I/O
L13N_2
I/O
L16P_2
GCLK14
W
I/O
L38P_3
I/O
L38N_3
I/O
L02P_2
M2
I/O
L03N_2
VCCO_2
I/O
L09N_2
VS0
GND
I/O
L12N_2
D6
I/O
L15P_2
GCLK12
I/O
L16N_2
GCLK15
Y
GND
I/O
L02N_2
CSO_B
I/O
L03P_2
I/O
L08P_2
I/O
L08N_2
I/O
L10P_2
I/O
L10N_2
VCCAUX
I/O
L15N_2
GCLK13
GND
Bank 2
Figure 24: FG400 Package Footprint (Top View)
DS529-4_03_011608
www.xilinx.com
107