XC3S200A-4VQG100C Datasheet, PDF (78/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
TMS 1
TDI 2
IO_L02P_3 3
IO_L01P_3 4
IO_L02N_3 5
IO_L01N_3 6
IO_L03P_3 7
IO_L03N_3 8
GND 9
IO_L04P_3 10
IO_L04N_3/VREF_3 11
IO_L05P_3/LHCLK0 12
IO_L05N_3/LHCLK1 13
VCCO_3 14
IO_L06P_3/LHCLK2 15
IO_L06N_3/LHCLK3 16
GND 17
IO_L07P_3/LHCLK4 18
IO_L08P_3/LHCLK6 19
IO_L07N_3/LHCLK5 20
IO_L08N_3/LHCLK7 21
VCCINT 22
VCCO_3 23
IO_L09P_3 24
IO_L09N_3 25
GND 26
IO_L10P_3 27
IO_L11P_3 28
IO_L10N_3 29
IO_L11N_3 30
IO_L12P_3 31
IO_L12N_3 32
IP_L13P_3 33
GND 34
IP_L13N_3/VREF_3 35
VCCAUX 36
X
Bank 0
Bank 2
108 VCCAUX
107 TDO
106 GND
105 IO_L11N_1
104 IO_L10N_1
103 IO_L11P_1
102 IO_L10P_1
101 IO_L09N_1
100 GND
99 IO_L09P_1
98 IO_L08N_1
97 IP_1/VREF_1
96 IO_L08P_1
95 VCCO_1
94 VCCINT
93 IO_L07N_1/RHCLK7
92 IO_L06N_1/RHCLK5
91 IO_L07P_1/RHCLK6
90 IO_L06P_1/RHCLK4
89 GND
88 IO_L05N_1/RHCLK3
87 IO_L05P_1/RHCLK2
86 VCCO_1
85 IO_L04N_1/RHCLK1
84 IO_L03N_1
83 IO_L04P_1/RHCLK0
82 IO_L03P_1
81 GND
80 IP_1/VREF_1
79 IO_1
78 IO_L01N_1/LDC2
77 IO_L02N_1/LDC0
76 IO_L01P_1/HDC
75 IO_L02P_1/LDC1
74 SUSPEND
73 _DONE
Figure 19: TQ144 Package Footprint (Top View)
DS529-4_10_031207
42
I/O: Unrestricted, general-purpose
user I/O
25
DUAL: Configuration pins, then
possible user I/O
2
INPUT: Unrestricted,
general-purpose input pin
30
CLK: User I/O, input, or global
buffer input
2
CONFIG: Dedicated configuration
pins
4 ^{JTAG: Dedicated JTAG port pins}
0 ^{N.C.: Not connected}
13 ^{GND: Ground}
SUSPEND: Dedicated SUSPEND
2 and dual-purpose AWAKE Power
Management pins
8
VREF: User I/O or input voltage
reference for bank
8
VCCO: Output voltage supply for
bank
4
VCCINT: Internal core supply
voltage (+1.2V)
4 ^{VCCAUX: Auxiliary supply voltage}
78
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DS529-4 (v2.0) August 19, 2010