XC3S200A-4VQG100C Datasheet, PDF (21/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Switching Characteristics
All Spartan-3A FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document are designated as Advance, Preliminary, or
Production, as shown in Table 16. Each category is defined
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device has been
characterized to provide full correlation between speed files
and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal
notification of any subsequent changes. Typically, the
slowest speed grades transition to Production before faster
speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
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Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A FPGA speed files (v1.41), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for these
files are shown in Table 16. For more complete, more
precise, and worst-case data, use the values reported by the
Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Table 16: Spartan-3A v1.41 Speed Grade Designation
Device
Advance Preliminary Production
XC3S50A
-4, -5
XC3S200A
-4, -5
XC3S400A
-4, -5
XC3S700A
-4, -5
XC3S1400A
-4, -5
Table 17 provides the recent history of the Spartan-3A
FPGA speed files.
Table 17: Spartan-3A Speed File Version History
ISE
Version Release
Description
1.41 ISE 10.1.03 Updated Automotive output delays
1.40 ISE 10.1.02 Updated Automotive input delays.
1.39 ISE 10.1.01 Added Automotive parts.
1.38 ISE 9.2.03i Added Absolute Minimum values.
Updated pin-to-pin setup and hold
times (Table 19), TMDS output
1.37 ISE 9.2.01i adjustment (Table 26) multiplier
setup/hold times (Table 34), and block
RAM clock width (Table 35).
ISE 9.2i; XC3S400A, all speed grades and all
previously temperature grades, upgraded to
1.36
available via Production
Answer
Record
AR24992
1.35
Answer
Record
AR24992
XC3S50A, XC3S200A, XC3S700A,
XC3S1400A, all speed grades and all
temperature grades, upgraded to
Production.
XC3S700A and XC3S1400A -4 speed
1.34 ISE 9.1.03i grade upgraded to Production. Updated
pin-to-pin timing numbers.
DS529-3 (v2.0) August 19, 2010
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