XC3S200A-4VQG100C Datasheet, PDF (109/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports both
the XC3S700A and the XC3S1400A FPGAs. There are
three pinout differences, as described in Table 86.
Table 83 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
The shaded rows indicate pinout differences between the
XC3S700A and the XC3S1400A FPGAs. The XC3S700A
has three unconnected balls, indicated as N.C. (No
Connection) in Table 83 and with the black diamond
character (‹) in Table 83 and Figure 25.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 83: Spartan-3A FG484 Pinout
Bank
Pin Name
FG484
Ball
0
IO_L01N_0
D18
0
IO_L01P_0
E17
0
IO_L02N_0
C19
0
IO_L02P_0/VREF_0
D19
0
IO_L03N_0
A20
0
IO_L03P_0
B20
0
IO_L04N_0
F15
0
IO_L04P_0
E15
0
IO_L05N_0
A18
0
IO_L05P_0
C18
0
IO_L06N_0
A19
0
IO_L06P_0/VREF_0
B19
0
IO_L07N_0
C17
0
IO_L07P_0
D17
0
IO_L08N_0
C16
0
IO_L08P_0
D16
0
IO_L09N_0
E14
0
IO_L09P_0
C14
0
IO_L10N_0
A17
0
IO_L10P_0
B17
0
IO_L11N_0
C15
Type
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 83: Spartan-3A FG484 Pinout(Continued)
Bank
Pin Name
FG484
Ball
Type
0
IO_L11P_0
D15
I/O
0
IO_L12N_0/VREF_0
A15 VREF
0
IO_L12P_0
A16
I/O
0
IO_L13N_0
A14
I/O
0
IO_L13P_0
B15
I/O
0
IO_L14N_0
E13
I/O
0
IO_L14P_0
F13
I/O
0
IO_L15N_0
C13
I/O
0
IO_L15P_0
D13
I/O
0
IO_L16N_0
A13
I/O
0
IO_L16P_0
B13
I/O
0
IO_L17N_0/GCLK5
E12 GCLK
0
IO_L17P_0/GCLK4
C12 GCLK
0
IO_L18N_0/GCLK7
A11 GCLK
0
IO_L18P_0/GCLK6
A12 GCLK
0
IO_L19N_0/GCLK9
C11 GCLK
0
IO_L19P_0/GCLK8
B11 GCLK
0
IO_L20N_0/GCLK11
E11 GCLK
0
IO_L20P_0/GCLK10
D11 GCLK
0
IO_L21N_0
C10
I/O
0
IO_L21P_0
A10
I/O
0
IO_L22N_0
A8
I/O
0
IO_L22P_0
A9
I/O
0
IO_L23N_0
E10
I/O
0
IO_L23P_0
D10
I/O
0
IO_L24N_0/VREF_0
C9
VREF
0
IO_L24P_0
B9
I/O
0
IO_L25N_0
C8
I/O
0
IO_L25P_0
B8
I/O
0
IO_L26N_0
A6
I/O
0
IO_L26P_0
A7
I/O
0
IO_L27N_0
C7
I/O
0
IO_L27P_0
D7
I/O
0
IO_L28N_0
A5
I/O
0
IO_L28P_0
B6
I/O
0
IO_L29N_0
D6
I/O
0
IO_L29P_0
C6
I/O
0
IO_L30N_0
D8
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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