XC3S200A-4VQG100C Datasheet, PDF (89/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
XC3S50A Differential I/O Alignment Differences
Also, some differential I/O pairs on the XC3S50A FPGA are
aligned differently than the corresponding pairs on the
XC3S200A or XC3S400A FPGAs, as shown in Table 74. All
the mismatched pairs are in I/O Bank 2. The shading
highlights the N side of each pair.
Table 74: Differential I/O Differences in FT256
FT256
Ball
Bank
XC3S50A
XC3S200A
XC3S400A
T3
IO_L04P_2/VS2 IO_L03N_2/VS2
N6
IO_L03N_2/VS1 IO_L04P_2/VS1
R5
IO_L06P_2
IO_L05N_2
T5
IO_L05N_2/D7 IO_L06P_2/D7
P10
2
IO_L14P_2/MOSI IO_L14N_2/MOSI
/CSI_B
/CSI_B
T10
IO_L14N_2
IO_L14P_2
R13
IO_L20P_2
IO_L18N_2
T14
IO_L18N_2
IO_L20P_2
XC3S50A Does Not Have BPI Mode Address Outputs
The XC3S50A FPGA does not generate the BPI-mode
address pins during configuration. Table 75 summarizes
these differences.
Table 75: XC3S50A BPI Functional Differences
FT256
Ball
Bank
XC3S50A
XC3S200A
XC3S400A
N16
IO_L03N_1
IO_L03N_1/A1
P16
IO_L03P_1
IO_L03P_1/A0
J13
IO_L10N_1
IO_L10N_1/A9
J12
IO_L10P_1
IO_L10P_1/A8
F13
IO_L20N_1
IO_L20N_1/A19
E14
IO_L20P_1
IO_L20P_1/A18
1
D15
IO_L22N_1
IO_L22N_1/A21
D16
IO_L22P_1
IO_L22P_1/A20
D14
IO_L23N_1
IO_L23N_1/A23
E13
IO_L23P_1
IO_L23P_1/A22
C15
IO_L24N_1
IO_L24N_1/A25
C16
IO_L24P_1
IO_L24P_1/A24
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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