DS695 Datasheet, PDF (9/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
words (1 word = 32 bits) per line by 512 lines per frame. Out of this 1024 x 512 memory space, only the
first 640 columns and 480 rows are displayed on the screen.
For a given row (0 to 479) and column (0 to 639), the pixel color information is encoded as shown in
Table 4.
Table 4: Pixel Color Encoding
Pixel Address
TFT Base Address +
(4096 * row) +
(4 * column)
Bits
[0:7]
[8:13]
[14:15]
[16:21]
[22:23]
[24:29]
[30:31]
Description
Undefined
Red Pixel Data:
000000 = darkest ^→ 111111 = brightest
Undefined
Green Pixel Data:
000000 = darkest ^→ 111111 = brightest
Undefined
Blue Pixel Data:
000000 = darkest ^→ 111111 = brightest
Undefined
XPS TFT Controller I/O Signals
The XPS TFT controller I/O signals are listed and described in Table 5.
Table 5: XPS TFT Controller I/O Signal Description
Port Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 MPLB_Clk
System
I
-
PLB master clock
P2 MPLB_Rst
P3 SPLB_Clk⁽¹⁾
System
I
System
I
-
PLB master reset
-
PLB slave clock
P4 SPLB_Rst
System
I
-
PLB slave reset
P5 MD_error
System
O
0
Master error detection indicator
(active high)
P6 IP2INTC_Irpt
System
O
0
Vysnc Pulse Interrupt
PLB Master Interface Signals
P7 M_request
PLB
O
0
Master bus request
P8 M_priority
PLB
O
0
Master bus request priority
P9 M_buslock
PLB
O
0
Master bus lock
P10 M_RNW
PLB
O
0
Master read not write
P11
M_BE(0:[C_MPLB_DWIDTH/8]-
1)
PLB
O
0
Master byte enables
P12 M_Msize(0:1)
PLB
O
0
Master data bus size
DS695 September 16, 2009
www.xilinx.com
9
Product Specification