DS695 Datasheet, PDF (14/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
XPS TFT Controller Design Parameters
To allow the user to create a XPS TFT controller that is uniquely tailored for the user’s system, certain
features are parameterizable in the XPS TFT controller design. This allows the user to have a design that
utilizes only the resources required by the system and runs at the best possible performance. The
features that are parameterizable in the XPS TFT controller core are shown in Table 6.
Table 6: XPS TFT Controller Design Parameters
Generic
Feature/Descripti
on
Parameter
Name
Allowable
Values
Default
Value
VHDL Type
XPS TFT Controller Parameter
G1 Target FPGA family C_FAMILY
spartan3a,
aspartan3a,
spartan3,
aspartan3,
spartan3e,
aspartan3e,
spartan3adsp,
aspartan3adsp,
spartan6, virtex4,
qvirtex4,
qrvirtex4, virtex5,
virtex5fx, virtex6,
virtex6cx
virtex4
string
G2
Base address of PLB
attached Video
memory
C_DEFAULT_TFT_
BASE_ADDR⁽¹⁾
valid address
0xF0000000 std_logic_vector
0 = DCR slave
G3
Controller Register
access interface
C_DCR_SPLB_SL interface
AVE_IF
1= PLB slave
1
interface
integer
G4
TFT interface
selection
C_TFT_INTERFAC 0 = VGA interface
E
1 = DVI interface
1
integer
G5
I2C Slave address of
external Chrontel
DVI transmitter
C_I2C_SLAVE_AD
DR
Valid 7 bit I2C
slave address
"1110110" std_logic_vector
DCR Interface Parameters
G6
DCR Slave Base
Address
C_DCR_BASEAD
DR
Valid Address
Valid 10-bit
address
std_logic_vector
G7
DCR Slave High
Address
C_DCR_HIGHADD
R
Valid Address
Valid 10-bit
address
std_logic_vector
PLB Master Interface Parameters
G8
Address bus width of
PLB
C_MPLB_AWIDTH
32
32
integer
G9
Data bus width of the
PLB
C_MPLB_DWIDTH
64, 128
64
integer
14
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DS695 September 16, 2009
Product Specification