DS695 Datasheet, PDF (16/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Optimal System Settings
It is recommended to have separate buses for the video memory access from the core and the rest of the
system. This will have sufficient bandwidth available between XPS TFT controller and PLB memory
device.
The native data width of XPS TFT controller is fixed to 64-bits. Optimal performance will be achieved
when the video memory interface width is greater than or equal to native data width of PLB master
interface (C_MPLB_SMALLEST_SLAVE ≥ C_MPLB_NATIVE_DWIDTH).
XPS TFT Controller Parameter - Port Dependencies
The dependencies between the XPS TFT controller core design parameters and I/O signals are
described in Table 7. In addition, when certain features are parameterized out of the design, the related
logic will no longer be a part of the design. The unused input signals and related output signals are set
to a specified value.
Table 7: XPS TFT Controller Design Parameter - Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G3
C_DCR_SPLB_SLAVE_IF P36 - P83
Affect DCR/PLB interface ports. If
C_DCR_SPLB_SLAVE_IF = 1, all DCR
-
ports are inactive. If
C_DCR_SPLB_SLAVE_IF = 0, all PLB
ports are inactive.
G4
C_TFT_INTERFACE
Affects TFT interface ports. If
P89 - P101
-
C_TFT_INTERFACE = 1, all VGA ports
are tied to ’0’. If C_TFT_INTERFACE =
0, all DVI ports are tied to ’0’.
G5
C_I2C_SLAVE_ADDR
Depends on C_TFT_INTERFACE.
-
G4
Required only when DVI interface is
selected.
G9
C_MPLB_DWIDTH
P10, P17,
P24
Affects the number of bits in PLB
-
master data bus
G13 C_SPLB_AWIDTH
P36
-
Affects number of bits in address bus
G14 C_SPLB_DWIDTH
P40, P43,
P50
-
Affects number of bits in slave data bus
G16 C_SPLB_MID_WIDTH
Affects the width of current master
P38
G18
identifier signals and depends on
log₂(C_SPLB_NUM_MASTERS) with a
minimum value of 1
G17
C_SPLB_NUM_MASTERS
P53, P54,
P55, P75
-
Affects the width of busy and error
signals
I/O Signals
P10
M_BE[0:
(C_MPLB_DWIDTH/8) - 1]
-
G9
Width varies with the size of the PLB
master data bus
P17
M_wrDBus[0:
C_MPLB_DWIDTH - 1]
-
G9
Width varies with the size of the PLB
master data bus
16
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DS695 September 16, 2009
Product Specification