DS695 Datasheet, PDF (13/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 5: XPS TFT Controller I/O Signal Description (Cont.)
Port Signal Name
Interface I/O
P87 TFT_VSYNC
P88 TFT_DE
P89 TFT_DPS
P90 TFT_VGA_CLK
P91 TFT_VGA_R[5:0]
P92 TFT_VGA_G[5:0]
P93 TFT_VGA_B[5:0]
P94 TFT_DVI_CLK_P
P95 TFT_DVI_CLK_N
P96 TFT_DVI_DATA[11:0]
TFT
O
TFT
O
TFT
O
TFT-VGA
O
TFT-VGA
O
TFT-VGA
O
TFT-VGA
O
TFT-DVI
O
TFT-DVI
O
TFT-DVI
O
P97 TFT_IIC_SCL_O
TFT-DVI
O
P98 TFT_IIC_SCL_I
P99 TFT_IIC_SCL_T
P100 TFT_IIC_SDA_O
TFT-DVI
I
TFT-DVI
O
TFT-DVI
O
P101 TFT_IIC_SDA_I
P102 TFT_IIC_SDA_T
TFT-DVI
I
TFT-DVI
O
Initial
State
1
0
0
0
0
0
0
0
0
0
0
-
1
0
-
1
Description
Vertical Sync (Active Low)
Data enable
TFT Display scan
TFT VGA clock⁽²⁾
TFT VGA Red pixel data⁽²⁾
TFT VGA Green pixel data⁽²⁾
TFT VGA Blue pixel data⁽²⁾
Differential TFT DVI clock⁽³⁾
Differential TFT DVI clock⁽³⁾
TFT DVI data⁽³⁾
I2C output clock to Chrontel
chip⁽⁴⁾
I2C input clock from Chrontel
chip⁽⁴⁾
3-state control for I2C clock⁽⁴⁾
I2C output data to Chrontel
chip⁽⁴⁾
I2C input data from Chrontel
chip⁽⁴⁾
3-state control for I2C data⁽⁴⁾
Notes:
1. This controller supports clock ratio of 1:1 or 1:2 only for slave interface clock(SPLB_Clk/DCR_Clk) and master
interface clock(MPLB_Clk).
2. VGA interface signals.
3. DVI interface signals.
4. I2C signals are used to configure Chrontel Video Encoder chip. These ports are active when DVI interface is
selected.
DS695 September 16, 2009
www.xilinx.com
13
Product Specification