DS695 Datasheet, PDF (1/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

DS695 September 16, 2009
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XPS Thin Film Transistor
(TFT) Controller (v2.00a)
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Product Specification
Introduction
The XPS Thin Film Transistor (TFT) controller is a
hardware display controller IP core capable of
displaying 256k colors. The XPS TFT controller
connects as a master on the PLB V4.6 (Processor Local
Bus with Xilinx simplification) and reads the video
pixel data from PLB attached video memory. This core
also connects as a slave to the PLB or DCR (Device
Control Register) bus for the register access. This core is
capable of configuring Chrontel CH-7301 DVI
Transmitter Chip through I2C interface.
Features
• Connects as 64-bit master on PLB V4.6 bus of 64 or
128 bits data width
• Connects as a 32-bit Slave on the DCR V2.9 bus or
PLB V4.6 bus of 32, 64 and 128 bits data width
• Supports DCR daisy chain protocol
• Parameterizable TFT interface for 18-bit VGA or
24-bit DVI
• Supports 25 Mhz TFT clock for display resolution of
640x480 pixels at 60 Hz refresh rate
• Supports configuration of external Chrontel DVI
Transmitter Chip through I2C interface
• Supports separate clock domain for PLB interface
and TFT interface
• Supports Vsync Interrupt and Status
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Virtex-4®, Virtex-4Q, Virtex-4QV,
Virtex-5, Virtex-5FX, Virtex-6,
Virtex-6CX, Spartan®-3E,
Automotive Spartan-3E,
Spartan-3, Automotive Spartan-3,
Spartan-3A, Automotive
Spartan-3A, Spartan-3A DSP,
Automotive Spartan-3A DSP,
Spartan-6
Version of core
xps_tft
v2.00a
Resources Used
Min
Max
SLICES
LUTs
FFs
Refer to the Table 13, Table 14,
Table 15 and Table 16
Block RAMs
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Special Features
N/A
Provided with Core
Documentation
Product Specification
Design File Formats Mixed
Constraints File
N/A
Verification
N/A
Instantiation
Template
N/A
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.3 or later
Verification
Mentor Graphics ModelSim v6.4b
or later
Simulation
Mentor Graphics ModelSim v6.4b
or later
Synthesis
XST 11.3or later
Support
Provided by Xilinx, Inc.
© 2008-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective
owners.
DS695 September 16, 2009
www.xilinx.com
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Product Specification