DS695 Datasheet, PDF (8/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Figure Top x-ref 5
tv
Vsynch
Hsyncs
tvp
tvb
thpb
480 H (Fixed)
tvf
1H
thf
DE
RGB
data
Invalid ^{D (X, 0)}
D (X, Y)
D (X, 479) _Invalid
DE
RGB
data
Invalid
D (0, Y)
D (X, Y)
tvp = Pulse Width = 2 h_syncs
tvb = Back Porch = 31 h_syncs
DE = Pixel Time = 640 TFT Clocks
tvf = Front Porch = 12 h_syncs
tv = Vsync Pusle = 525 h_sync
thpb = Back Porch to Valid Data = thp + thb
thf = Hsync Front Porch
Display period is 480 h_syncs
Figure 5: Vertical Data
D (639, Y)
Invalid
DS695_05_020509
Video Memory
It is important to design the system so that there is a sufficient bandwidth available between the XPS
TFT controller and the PLB memory device to meet the video bandwidth requirements of the TFT.
Furthermore, there must be enough bandwidth available for rest of the system. If the bandwidth
requirement of rest of the system is more, the TFT clock frequency can be reduced. However, reducing
the TFT clock frequency also lowers the refresh rate of the screen. This may lead to a noticeable flicker
on the screen if the TFT clock is too slow. The PLB master interface logic has the ability to skip reading
a line of data if it fails to finish reading data from a previous line because of shortage of PLB bandwidth.
This prevents the XPS TFT controller losing synchronization between the PLB and TFT interface logic.
Note that extreme shortage of available bandwidth for the XPS TFT controller may cause the screen to
appear unstable as stale lines of video data are displayed on the screen.
The video memory is expected to be arranged so that each RGB pixel is represented by a 32-bit word in
memory. The video memory should be stored in a 2 MB region of memory consisting of 1024 data
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DS695 September 16, 2009
Product Specification