DS695 Datasheet, PDF (25/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
The XPS TFT controller resource utilization for various parameter combinations measured with
Virtex-5 as the target device are detailed in Table 14.
Table 14: Performance and Resource Utilization Benchmarks on Virtex-5 FPGA (xc5vfx70-ff1136-1)
Parameter Values
Device Resources
Performance
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Slices
Slice
Flip-Flops
LUTs F_MAX (MHz)
0
0
276
414
479
154
0
1
389
498
598
152
1
0
364
462
478
153
1
1
412
546
596
152
The XPS TFT controller resource utilization for various parameter combinations measured with the
Spartan-3 FPGA as the target device are detailed in Table 15.
Table 15: Performance and Resource Utilization Benchmarks on the Spartan-3 FPGA
(xc3sd1800a-fg676-4)
Parameter Values
Device Resources
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE Slices
Slice
Flip-Flops
LUTs
0
0
521
411
504
0
1
591
495
609
1
0
495
459
504
1
1
617
543
609
Performance
F_MAX (MHz)
102
102
102
102
The XPS TFT controller resource utilization for various parameter combinations measured with the
Virtex-6 FPGA as the target device are detailed in Table 16.
Table 16: Performance and Resource Utilization Benchmarks on Virtex-6 FPGA (xc6vlx75ft-ff784-1)
Parameter Values
Device Resources
Performance
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE Slices
Slice
Flip-Flops
LUTs F_MAX (MHz)
0
0
192
500
537
160
0
1
202
567
639
160
1
0
232
514
585
160
1
1
224
581
709
160
DS695 September 16, 2009
www.xilinx.com
25
Product Specification