DS695 Datasheet, PDF (15/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 6: XPS TFT Controller Design Parameters (Cont.)
Generic
Feature/Descripti
on
Parameter
Name
Allowable
Values
Default
Value
VHDL Type
G10
Data width of the
PLB attached video
memory
C_MPLB_SMALLE
ST_SLAVE
32, 64, 128
64
integer
G11
Internal native data
width of master
interface
C_MPLB_NATIVE_
DWIDTH
64
64
integer
PLB Slave Interface Parameters
G12
XPS TFT controller
Base Address
C_SPLB_BASEAD
DR
Valid Address⁽³⁾
None⁽²⁾
std_logic_vector
G13
XPS TFT controller
High Address
C_SPLB_HIGHAD
DR
Valid Address⁽³⁾
None⁽²⁾
std_logic_vector
G14
PLB slave interface
address width
C_SPLB_AWIDTH
32
32
integer
G15
PLB slave interface
data width
C_SPLB_DWIDTH
32, 64, 128
32
integer
Selects
G16 point-to-point or
C_SPLB_P2P
shared PLB topology
0 = Shared Bus
Topology
0
integer
log₂(C_SPLB_
G17
PLB Master ID bus C_SPLB_MID_WI NUM_MASTERS
width
DTH
) with a minimum
1
integer
value of 1
G18
Number of PLB
Masters
C_SPLB_NUM_M
ASTERS
1 - 16
1
integer
G19
Width of the internal C_SPLB_NATIVE_
slave data bus
DWIDTH
32
32
integer
Notes:
1. C_DEFAULT_TFT_BASE_ADDR specifies the base address of PLB attached video memory. This base
address of video memory must be aligned on a 2MB boundary (i.e. only upper 11 bits are valid, the remaining
address bits must be always ’0’). The controller will only use 11 MSB of this base address to read data from the
video memory.
2. No default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler
error will be generated.
3. C_SPLB_BASEADDR must be a multiple of the range size, where the range size is C_SPLB_HIGHADDR -
C_SPLB_BASEADDR + 1 and must be a power of two. The range size must be large enough to accommodate
all of the registers.
Allowable Parameter Combinations
The address-range size specified by C_SPLB_BASEADDR and C_SPLB_HIGHADDR must be a power
of 2, and must be at least 0x10.
The address specified by C_DEFAULT_TFT_BASE_ADDR must be aligned on a 2MB boundary. Only
11 MSB bits should have valid address, the remaining address bits must be always ’0’.
The PLB slave interface is only included in the design if C_DCR_SPLB_SLAVE_IF is set to 1. When
C_DCR_SPLB_SLAVE_IF = 0, DCR slave interface is included in the design and all the PLB ports are
unused.
DS695 September 16, 2009
www.xilinx.com
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Product Specification