DS695 Datasheet, PDF (7/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Hsync Timing
The Hsync is active low signal and the complete time period of the Hsync is 800 TFT clocks. Out of the
800 TFT clock period, the active pixel data qualified by the active high DE signal is of 640 TFT clocks.
The Hsync pulse period is of 96 TFT clocks. The time period between the Hsync pulse and start of
active data is called as back porch which is of 48 TFT clocks. The time period between the end of active
data and start of new Hsync pulse is called as front porch which is of 16 TFT clocks. The Hsync timing
with respect to the TFT clock is shown in Figure 4.
Figure Top x-ref 4
th
Hsynch
thp
thb
640 Clk (Fixed)
thf
CLK
DE
RGB
data
Invalid
D (0, Y) D (1, Y)
thp = Pulse Width = 96 TFT Clocks
thb = Back Porch = 48 TFT Clocks
DE = Pixel Time = 640 TFT Clocks
thf = Front Porch = 16 TFT Clocks
th = Hsync Pulse = 800 TFTClocks
Figure 4: Horizontal Data
D (639, Y) Invalid
DS695_04_020509
Vsync Timing
The Vsync is active low signal and the complete time period of the Vsync is of 525 h_syncs. Out of the
525 h_syncs, the Vsync pulse period is of 2 h_syncs, the active display period is of 480 h_syncs, the back
porch period is of 31 h_syncs and the front porch period is of 12 h_syncs. The Vsync timing with respect
to the Hsync is shown in Figure 5.
DS695 September 16, 2009
www.xilinx.com
7
Product Specification