DS695 Datasheet, PDF (12/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 5: XPS TFT Controller I/O Signal Description (Cont.)
Port Signal Name
Interface I/O
P62 PLB_busLock
P63 PLB_MSize
P64 PLB_lockErr
P65 PLB_wrBurst
P66 PLB_rdBurst
P67 PLB_wrPendReq
P68 PLB_rdPendReq
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
P69 PLB_wrPendPri[0:1]
PLB
I
Initial
State
-
-
-
-
-
-
-
-
P70 PLB_rdPendPri[0:1]
PLB
I
-
P71 PLB_reqPri[0:1]
P72 PLB_TAttribute[0:15]
PLB
I
-
PLB
I
-
P73 Sl_wrBTerm
PLB
O
0
P74 Sl_rdWdAddr[0:3]
PLB
O
0
P75 Sl_rdBTerm
PLB
O
0
P76
Sl_MIRQ[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
DCR Slave Interface Signals
P77 DCR_Clk⁽¹⁾
DCR
I
-
P78 DCR_Rst
DCR
I
-
P79 DCR_Read
DCR
I
-
P80 DCR_Write
P81
DCR_ABus[0 :
C_SDCR_AWIDTH-1]
P82
DCR_Sl_DBus[0 :
C_SDCR_DWIDTH-1]
P83
Sl_DCR_DBusout[0 :
C_SDCR_DWIDTH-1]
P84 Sl_dcrAck
P85 SYS_TFT_Clk
P86 TFT_HSYNC
DCR
I
-
DCR
I
-
DCR
I
-
DCR
O
0
DCR
O
0
TFT Interface Signals
TFT
I
-
TFT
O
1
Description
PLB bus lock
PLB data bus width indicator
PLB lock error
PLB burst write transfer
PLB burst read transfer
PLB pending bus write request
PLB pending bus read request
PLB pending write request
priority
PLB pending read request
priority
PLB current request priority
PLB transfer attribute
Slave terminate write burst
transfer
Slave read word address
Slave terminate read burst
transfer
Master interrupt request
DCR clock
DCR reset
DCR read request from DCR
master
DCR write request from DCR
master
DCR address bus from DCR
master
DCR slave data bus from DCR
master
Slave DCR data bus out
Slave DCR acknowledge
TFT clock input
Horizontal Sync (Active Low)
12
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DS695 September 16, 2009
Product Specification