DS695 Datasheet, PDF (10/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 5: XPS TFT Controller I/O Signal Description (Cont.)
Port Signal Name
Interface I/O
Initial
State
Description
P13 M_size(0:3)
PLB
O
0
Master transfer size
P14 M_type(0:2)
PLB
O
0
Master transfer type
P15 M_ABus(0:31)
PLB
O
0
Master address bus
P16 M_wrBurst
PLB
O
0
Master burst write transfer
indicator
P17 M_rdBurst
PLB
O
0
Master read write transfer
indicator
P18
M_wrDBus(0:C_MPLB_DWIDT
H-1)
PLB
O
0
Master write data bus
P19 PLB_MSize(0:1)
PLB
I
-
PLB master slave data bus port
width
P20 PLB_MaddrAck
PLB
I
-
PLB master address
acknowledge
P21 PLB_Mrearbitrate
PLB
I
-
PLB master bus rearbitrate
indicator
P22 PLB_MTimeout
PLB
I
-
PLB master bus time out
P23 PLB_MRdErr
PLB
I
-
PLB master slave read error
indicator
P24 PLB_MWrErr
PLB
I
-
PLB master slave write error
indicator
P25
PLB_MRdDBus(0:C_MPLB_D
WIDTH-1)
PLB
I
-
PLB master read data bus
P26 PLB_MRdDAck
PLB
I
-
PLB master read data
acknowledge
P27 PLB_MWrDAck
PLB
I
-
PLB master write data
acknowledge
P28 PLB_RdBTerm
PLB
I
-
PLB master terminate read burst
indicator
P29 PLB_MWrBTerm
PLB
I
-
PLB master terminate write burst
indicator
Unused PLB Master Interface Signals
P30 M_TAttribute(0 to 15)
PLB
O
0
Master transfer attribute
P31 M_lockerr
PLB
O
0
Master lock error indicator
P32 M_abort
PLB
O
0
Master abort bus request
indicator
P33 M_UABus(0:31))
PLB
O
0
Master upper address
P34 PLB_MBusy
PLB
I
-
PLB master busy signal
P35 PLB_MIRQ
PLB
I
-
PLB master interrupt indicator
P36 PLB_RdWdAddr(0:3)
PLB
I
-
PLB master read word address
10
www.xilinx.com
DS695 September 16, 2009
Product Specification