DS695 Datasheet, PDF (2/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Functional Description
The XPS TFT controller is a hardware display controller for a 640x480 resolution display screen. This
core is capable of displaying up to 256K colors through VGA or DVI interface. The design contains PLB
master interface that reads video data from a PLB attached memory device and displays the data onto
the TFT screen. The design also contains parameterizable DCR and PLB slave interface. If the
parameter C_DCR_SPLB_SLAVE_IF is set to 1, the controller can be configured using PLB slave
interface, else it can be configured through DCR slave interface. This controller also provide I2C
interface to configure Chrontel CH7301C video encoder chip when the DVI interface is selected. The
XPS TFT controller block diagram is shown in Figure 1.
Figure Top x-ref 1
DCR_Clk
DCR_Rst
XPS TFT Controller
2
DCR Slave
Interface
Module
TFT Controller
Slave Register
Logic
Register
Access
Control
1
PLB Slave
AR
Interface
CR
Module
IP2INTC_Irpt
PLB
Master
Interface
Module
TFT Control
Logic
HSYNC
VSYNC
Control
Line Buffer
TFT Interface
Logic
4
V
G
A
3
D
V
I
5
I2C Interface
for Chrontel
Ch7301
Configuration
TFT Interface
Signals
TFT_DPS
TFT_DE
TFT_VSYNC
TFT_HSYNC
TFT_VGA_CLK
TFT_VGA_R
TFT_VGA_G
TFT_VGA_B
TFT_DVI_CLK_P
TFT_DVI_CLK_N
TFT_DVI_DATA
TFT_IIC_SCL
TFT_IIC_SDA
SYS_TFT_Clk
PLB Clock Domain TFT Clock Domain
Note:
1. PLB Slave Interface is included in the design if the parameter C_DCR_SPLB_SLAVE_IF = 1.
2. DCR slave interface is part of Slave Regiter Logic and included in the design if the parameter
C_DCR_SPLB_SLAVE_IF = 0.
3. DVI interface is included in the design if the parameter C_TFT_INTERFACE = 1.
4. VGA interface is included in the design if the parameter C_TFT_INTERFACE = 0.
5. This logic is included in the design if C _TFT_INTERFACE = 1.
Figure 1: XPS TFT Controller Block Diagram
DS695_01_020509
2
www.xilinx.com
DS695 September 16, 2009
Product Specification