DS695 Datasheet, PDF (24/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Figure Top x-ref 15
DPLB0
PPC
IPLB0
PLBv46
PIM
MPMC
PLBv46
PIM
Memory
PLB Slave 1
PLB Slave 2
Master
Interface
XPS TFT
Controller
Slave
Interface
DS695_14_020509
Figure 15: PowerPC Processor System with Separate PLB Buses for XPS TFT Master and Slave Interface
Design Implementation
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE Facts
Table.
Device Utilization and Performance Benchmarks
Since the XPS TFT controller core will be used with other design modules in the FPGA, the utilization
and timing numbers reported in this section are estimates only. When the XPS TFT controller core is
combined with other designs in the system, the utilization of FPGA resources and timing of the XPS
TFT controller design will vary from the results reported here.
The XPS TFT controller resource utilization for various parameter combinations measured with
Virtex-4 FPGA as the target device are detailed in Table 13.
Table 13: Performance and Resource Utilization Benchmarks on the Virtex-4 FPGA (xc4vlx25-ff668-10)
Parameter Values
Device Resources
Performance
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Slices
Slice
Flip-Flops
LUTs F_MAX (MHz)
0
0
410
414
544
143
0
1
611
498
660
139
1
0
514
464
543
139
1
1
628
546
660
140
24
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DS695 September 16, 2009
Product Specification