DS695 Datasheet, PDF (11/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 5: XPS TFT Controller I/O Signal Description (Cont.)
Port Signal Name
Interface I/O
Initial
State
PLB Slave Interface Signals
P37
PLB_ABus[0:
C_SPLB_AWIDTH - 1]
PLB
I
-
P38 PLB_PAValid
PLB
I
-
P39
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
PLB
I
-
P40 PLB_RNW
PLB
I
-
P41
PLB_BE[0:
(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
P42 PLB_size[0:3]
PLB
I
-
P43 PLB_type[0:2]
PLB
I
-
P44
PLB_wrDBus[0:
C_SPLB_DWIDTH - 1]
PLB
I
-
P45 Sl_addrAck
PLB
O
0
P46 Sl_SSize[0:1]
PLB
O
0
P47 Sl_wait
PLB
O
0
P48 Sl_rearbitrate
PLB
O
0
P49 Sl_wrDAck
PLB
O
0
P50 Sl_wrComp
PLB
O
0
P51
Sl_rdDBus[0:
C_SPLB_DWIDTH - 1]
PLB
O
0
P52 Sl_rdDAck
PLB
O
0
P53 Sl_rdComp
PLB
O
0
P54
Sl_MBusy[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
P55
Sl_MWrErr[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
P56
Sl_MRdErr[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Unused PLB Slave Interface Signals
P57 PLB_UABus[0: 31]
PLB
I
-
P58 PLB_SAValid
PLB
I
-
P59 PLB_rdPrim
PLB
I
-
P60 PLB_wrPrim
P61 PLB_abort
PLB
I
-
PLB
I
-
Description
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
Slave address acknowledge
Slave data bus size
Slave wait
Slave bus rearbitrate
Slave write data acknowledge
Slave write transfer complete
Slave read data bus
Slave read data acknowledge
Slave read transfer complete
Slave busy
Slave write error
Slave read error
PLB upper address bits
PLB secondary address valid
PLB secondary to primary read
request indicator
PLB secondary to primary write
request indicator
PLB abort bus request
DS695 September 16, 2009
www.xilinx.com
11
Product Specification