DS695 Datasheet, PDF (20/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Module and set the Hsync and Vsync to their default value causing the display to enter in sleep mode.
The bit assignment in the TFT control register is shown in Figure 7 and described in Table 11.
Figure Top x-ref 7
Reserved
TDE
0
29 30 31
Figure 7: Control Register
DPS
DS695_07_020509
Table 11: Control Register description
Bits
Name
Core
Access
Reset
Value
[0:29]
Reserved
N/A
N/A
[30]
DPS
R/W
0
[31]
TDE
R/W
1
Description
Reserved
Display Scan Control Bit
0 = Set DPS output bit to 0. This sets the display to use
normal scan direction.
1 = Set DPS output bit to 1. This sets the display to use
reverse scan direction (rotates screen 180 degrees).
TFT Display Enable Bit
0 = Disable TFT display. This resets the TFT controller
and stops Vsync/Hsync signals causing display to go in
sleep mode.
1 = Enable TFT display. This causes the TFT controller to
operate normally.
Interrupt Enable and Status Register (IESR)
TFT Interrupt Enable and Status register is a 32-bit read/write register. This register contains Vsync
interrupt enable bit and the status bit. If Vsync interrupt is enabled, core generates interrupt for Vsyn
pulse every frame. For every rising edge of Vsync pulse, core set status bit to indicate that core has
displayed the current frame completely and accepted the new address from the AR. This status bit gets
cleared for every write access to the AR. The bit assignment in the IESR is shown in Figure 8 and
described in Table 12.
Figure Top x-ref 8
Reserved
Interrupt
Enable (I) ^Status(S)
0
27 28 29 30 31
DS695_15_020509
Figure 8: Interrupt Enable and Status Register
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DS695 September 16, 2009
Product Specification