DS695 Datasheet, PDF (19/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 9: XPS TFT Controller Internal Registers access through DCR
Base Address + Offset Register
(hex)
Name
Access
Default Value
(hex)
Description
C_DCR_BASEADDR + 0
TFT address register which
AR
Read/Write
C_DEFAULT_TFT_
BASE_ADDR
specifies the base address
of the video memory from
which the controller fetches
the data
C_DCR_BASEADDR + 1
CR
Read/Write
0x1
TFT control register
C_DCR_BASEADDR + 2
IESR
Read/Write
0x0
Vsync interrupt enable and
status register.
C_DCR_BASEADDR + 3
Reserved
NA
NA
Reserved for future use
Address Register (AR)
TFT Base Address Register specifies the upper 11-bits of base address of the video memory. This is the
address of PLB accessible memory device that acts as a video memory. This address must be aligned on
a 2MB boundary (i.e. only upper 11 bits are writable, the remaining address bits are always ’0’) as
shown in Figure 6 and described in Table 10.
Figure Top x-ref 6
11 MSB of Video
Memory address
Reserved
0
10 11
31
DS695_06_020509
Figure 6: Address Register
Table 10: Address Register Description
Bits
Name
Core
Access
Reset Value
Description
[0:10]
TFT base
address
R/W
C_DEFAULT_TFT_BASE_
ADDR[0:10]
Specifies the base address of the video
memory from which the controller fetched
the data
[11:31] Reserved
N/A
N/A
Reserved
Control Register (CR)
TFT Control Register contains the control bits to configure the controller for TFT scanning mode and
TFT display on/off. Writing ’0’ in TFT display enable bit resets the TFT controller. In the reset state,
controller stops requesting data from the video memory by applying reset to the Master Interface
DS695 September 16, 2009
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Product Specification