DS695 Datasheet, PDF (21/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 12: Interrupt Enable and Status Register description
Bits
Name
Core
Access
Reset
Value
Description
[0:27]
Reserved
N/A
N/A
Reserved
[28]
Interrupt
Enable
R/W
Vsync Interrupt Enable
0
0 = Disable Vsync pulse interrupt.
1 = Enable Vsync pulse interrupt.
[29:30] Reserved
N/A
N/A
Reserved
[31]
Status
R/W
Vsync and address latch status bit
0 = Core is displaying current frame.
0
1 = Vsync pulse is active. Also indicate that previous
frame is displayed completely and core has accepted
new address from the AR.
XPS TFT Controller Timing Diagrams
XPS TFT Master Burst Read on PLB attached Memory
The XPS TFT burst read transaction on PLB are shown in Figure 9.
Figure Top x-ref 9
Cycles 0 1 2 3 4 5 6 7 8 9 10 111213 1415 16 1718 1920 2122 23 24 2526 27 282930 31 3233 34 353637 38 39
MPLB_Clk
M_request
M_RNW
M_BE[0:7]
F0
F0
M_size[0:3]
B
B
M_Abus[0:31]
A0
A0+80
M_rdBurst
PLB_MAddrAck
PLB_MRdDBus[0:63]
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D16 D17 D18 D19 D20 D21
PLB_MRdDAck
DS695_08_020509
Figure 9: XPS TFT Burst Read Transaction on PLB
XPS TFT Register Read/Write through PLB slave interface
Figure 10 shows XPS TFT controller register access through PLB slave interface.
Figure Top x-ref 10
Cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SPLB_Clk
PLB_Abus[0:31]
A0
A0
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
F
PLB_wrDBus[0:31]
D0
Sl_AddrAck
Sl_rdDAck
Sl_wrDAck
Sl_rdDBus[0:31]
D0
DS695_09_020509
Figure 10: XPS TFT Register Read/Write Through PLB Slave Interface
DS695 September 16, 2009
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Product Specification