DS695 Datasheet, PDF (17/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 7: XPS TFT Controller Design Parameter - Port Dependencies (Cont.)
Generic
or Port
Name
Affects Depends
Relationship Description
P24
PLB_MRdDBus[0:
C_MPLB_DWIDTH - 1]
-
G9
Width varies with the size of the PLB
master data bus
P36
PLB_ABus[0:
C_SPLB_AWIDTH - 1]
-
G14
Width varies with the size of the PLB
address bus
P38
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
-
G17
Width varies with the size of the PLB
master identifier bus
P40
PLB_BE[0:
(C_SPLB_DWIDTH/8)-1]
-
G15
Width varies with the size of the PLB
slave data bus
P43
PLB_wrDBus[0:
C_SPLB_DWIDTH - 1]
-
G15
Width varies with the size of the PLB
slave data bus
P50
Sl_rdDBus[0:
C_SPLB_DWIDTH - 1]
-
G15
Width varies with the size of the PLB
slave data bus
Sl_MBusy[0:
P53 C_SPLB_NUM_MASTERS
-
- 1]
G18
Width varies with the number of PLB
masters
Sl_MWrErr[0:
P54 C_SPLB_NUM_MASTERS
-
- 1]
G18
Width varies with the number of PLB
masters
Sl_MRdErr[0:
P55 C_SPLB_NUM_MASTERS
-
- 1]
G18
Width varies with the number of PLB
masters
Sl_MIRQ[0:
P75 C_SPLB_NUM_MASTERS
-
- 1]
G18
Width varies with the number of PLB
masters
P36 -
P75
PLB Slave Interface ports
G3
Ports are unused when
C_DCR_SPLB_SLAVE_IF = 0
P76 -
P82
DCR Interface ports
G3
Ports are unused when
C_DCR_SPLB_SLAVE_IF = 1
P88 TFT_VGA_CLK
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 1
P89 TFT_VGA_R
-
G4
Ports tied to ’0’ when
C_TFT_INTERFACE = 1
P90 TFT_VGA_G
-
G4
Ports tied to ’0’ when
C_TFT_INTERFACE = 1
P91 TFT_VGA_B
-
G4
Ports tied to ’0’ when
C_TFT_INTERFACE = 1
P92 TFT_DVI_CLK_P
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 0
P93 TFT_DVI_CLK_N
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 0
P94 TFT_DVI_DATA
-
G4
Ports tied to ’0’ when
C_TFT_INTERFACE = 0
DS695 September 16, 2009
www.xilinx.com
17
Product Specification