DS695 Datasheet, PDF (3/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
The major modules of XPS TFT controller are described in subsequent sections.
These modules are:
• PLB Master Interface Module
• PLB Slave Interface Module
• Slave Register Logic
• TFT Control Logic
• Line Buffer
• HSYNC VSYNC Control
• TFT Interface Logic
PLB Master Interface Module
The PLB Master Interface Module provides master interface between TFT controller and the PLB. TFT
controller reads pixel data from an external PLB memory device through PLB Master Interface Module.
This module takes care of bus interface signals, bus protocol and other interface issues. The master
interface native data width is fixed to 64-bits. The C_MPLB_SMALLEST_SLAVE size should be same as
the PLB attached memory data width.
PLB Slave Interface Module
The PLB Slave Interface Module provides interface between Slave Register Logic and PLB bus.This
interface is included in the design if parameter C_DCR_SPLB_SLAVE_IF is set to 1. The XPS TFT
controller registers can be accessed through PLB using this interface. The XPS TFT controller core only
supports 1:1 and 1:2 clock ratio for SPLB to MPLB clocks.
Slave Register Logic
The Slave Register Logic module consists of Address Register (AR), Control Register (CR) and logic to
provide the access to these registers using either PLB or DCR interface. The DCR slave interface logic is
included in the design if the parameter C_DCR_SPLB_SLAVE_IF is set to 0. The Address Register
allows user to change the base address of video memory to be read from. This allows video frames to
be fetched from other memory locations without being seen on the display. The user can change the
video memory base address to display a different frame when it is ready. The Control Register allows
the display to be rotated by 180 degrees or turned off by configuring the control bits.
TFT Control Logic
The TFT Control Logic module generates read request to PLB Master Interface Module to get pixel data
from an external PLB memory device. This module synchronizes the signals crossing the different clock
domains. The TFT control logic generates master read request, address for the video memory and reads
the pixel data for each display line using a series of 16-double word burst transactions. The pixel data
is stored in an internal line buffer and then sent out to TFT display with the necessary timing to
correctly display the image. This process repeats continuously over every line and frame to be
displayed on the 640x480 TFT screen. The data flow diagram from PLB to TFT is shown in Figure 2.
When the display is turned off by clearing the display enable bit in the Control Register, the TFT
controller issues reset to all the counters and stops requesting data from the video memory by applying
reset to the Master Interface Module. In the reset state, the controller sets the Hsync and Vsync to their
default value causing the display to enter in sleep mode.
DS695 September 16, 2009
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Product Specification