DS695 Datasheet, PDF (18/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Table 7: XPS TFT Controller Design Parameter - Port Dependencies (Cont.)
Generic
or Port
Name
Affects Depends
Relationship Description
P95 TFT_IIC_SCL_O
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 0
P96 TFT_IIC_SCL_I
-
G4
Port is un-used when
C_TFT_INTERFACE = 0
P97 TFT_IIC_SCL_T
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 0
P98 TFT_IIC_SDA_O
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 0
P99 TFT_IIC_SDA_I
-
G4
Port is un-used when
C_TFT_INTERFACE = 0
P100 TFT_IIC_SDA_T
-
G4
Port tied to ’0’ when
C_TFT_INTERFACE = 0
XPS TFT Controller Register Description
There are four internal registers available in the XPS TFT controller design. These registers can be
accessed through either PLB slave interface or DCR slave interface based on the parameter setting
C_DCR_SPLB_SLAVE_IF. The memory map of the XPS TFT controller design is determined by setting
the C_SPLB_BASEADDR/C_DCR_BASEADDR parameter. The internal registers of the XPS TFT
controller are at a fixed offset from the base address on 32-bit boundary. Writing into the reserved
registers has no effect. Reading from the reserved registers returns zero. All registers are defined for
32-bit access only. When the PLB slave interface is selected, any partial word write access (byte,
half-word) has no effect on the registers and any partial word read access (byte, half-word) returns
zero. All the partial access to the core register returns bus error. The XPS TFT controller internal
registers and their offset for the PLB interface and the DCR interface are listed in Table 8 and Table 9.
Table 8: XPS TFT Controller Internal Registers access through PLB
Base Address + Offset Register
(hex)
Name
Access
Default Value
(hex)
Description
C_SPLB_BASEADDR + 0
TFT address register which
AR
Read/Write
C_DEFAULT_TFT_
BASE_ADDR
specifies the base address
of the video memory from
which the controller fetches
the data
C_SPLB_BASEADDR + 4
CR
Read/Write
0x1
TFT control register
C_SPLB_BASEADDR + 8
IESR
Read/Write
0x0
Vsync interrupt enable and
status register.
C_SPLB_BASEADDR + C Reserved
NA
NA
Reserved for future use
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DS695 September 16, 2009
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