DS695 Datasheet, PDF (4/27 Pages) Xilinx, Inc – XPS Thin Film Transistor

XPS Thin Film Transistor (TFT) Controller (v2.00a)
Figure Top x-ref 2
PLB Clock Domain
TFT Clock Domain
Video
Memory
TFT
Control
Logic
Get Line
PLB
Master
Interface
Module
9 Column Addr
12 Red Data
12 Green Data
Line
Buffer
10 Column Addr
6 Red Data
6 Green Data
TFT
Interface
Logic
Video Signal
To TFT
Display
12 Blue Data
6 Blue Data
Figure 2: Data Flow Diagram
DS695_02_020509
Line Buffer
The XPS TFT controller allows PLB clock and TFT video clock to be asynchronous to each other. The
line buffer module includes synchronization logic to allow control signals to be passed between
asynchronous PLB and TFT clock domains. This module consists of a dual port BRAM of size 1KB x 18
bit which is used as the line buffer to pass video data between the two clock domains. Out of 64-bit PLB
data, the 36-bit of RGB data gets written to the BRAM.
HSYNC/VSYNC Control
This module generates the necessary timing of all the video synchronization signals including back
porch and front porch timing for Hsync and Vsync. See Video TimingVideo Timing section for more
information.
TFT Interface Logic
The TFT interface logic driving the TFT display operates in the same clock domain as the video clock.
It reads out the pixel data from the dual port line buffer and transmits it to the TFT. This module
consists of logic to transmit the pixel data in either VGA or DVI format based on the parameter
C_TFT_INTERFACE and the logic to configure the Chrontel CH-7301 video encoder chip. The Hsync,
Vsync and DE signals are common for both the interfaces. The VGA, DVI and Chrontel I2C interfaces
are described below.
VGA Interface
The VGA interface logic is included in the design if the parameter C_TFT_INTERFACE is set to 0. The
18-bit RGB pixel data is transmitted to the VGA ports and logic ’0’ is transmitted to all DVI ports.
DVI Interface
The DVI interface logic is included in the design if the parameter C_TFT_INTERFACE is set to 1. The
18-bit RGB data is converted into 24-bit pixel data by padding zeros in between the RGB data. This
24-bit pixel data is transmitted to the 12-bit DVI data port by clocking the data on both edges using
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DS695 September 16, 2009
Product Specification