W83977ATF Datasheet, PDF (90/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)
These registers control flow control mode operation as shown in the following table.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FC_MD FC_MD2 FC_MD1 FC_MD0
-
FC_DSW EN_FD EN_BRFC EN_FC
Reset Value
0
0
0
0
0
0
0
0
Bit 7~5
Bit 4:
Bit 3:
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced
HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allows user to swap DMA channel for transmitter or receiver when flow
control is enforced.
FC_DSW
Next Mode After Flow Control Occurred
0
Receiver Channel
1
Transmitter Channel
Bit 2:
Bit 1:
Bit 0:
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
4.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2
Default Value
1
1
1
0
1
1
Bit 1
SRR1
0
Bit 0
SRR0
0
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Publication Release Date:April 1998
Revision 0.52