W83977ATF Datasheet, PDF (173/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
Bit
Name
0
TMR_STS
1-3 Reserved
4
BM_STS
5
GBL_STS
Reserved
Description
This bit is the timer carry status bit. This bit is set anytime the bit 23 of the
24-bit counter changes (whenever the MSB changes from low to high or high
to low). When TMR_EN and TMR_STS are set, a power magement event is
raised. This bit is only set by hardware and can only be cleared by writing a
1 to this bit position. Writing a 0 has no effect.
Reserved.
This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a
0 has no effect.
This is the global status bit. This bit is set when the BIOS wants the
attention of the
can only be cleared by writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
Reserved. These bits always return zeros.
Register Location:
<
> + 1H System I/O Space
Default Value:
Attribute:
Read/write
8 bits
765
43
21
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WAK_STS
Bit
Name
0-6 Reserved
7
WAK_STS
event occurs. Upon setting this bit, the sleeping/working state machine will
transition the system to the working state. This bit is only set by hardware and
, or by the sleeping/working state
no effect. When the WAK_STS is cleared and all devices are in sleeping
state, the whole chip enters the sleeping state.
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Publication Release Date:April 1998
Revision 0.53