W83977ATF Datasheet, PDF (151/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
CRF3 (WDT_CTRL0, Default 0x00)
Watch Dog Timer Control Register #0
Bit 7 - 4: Reserved
Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
= 1 Enable
= 0 Disable
Bit 2: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt
Bit 1: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt
Bit 0: Reserved.
CRF4 (WDT_CTRL1, Default 0x00)
Watch Dog Timer Control Register #1
Bit 7 - 4: Reserved
Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
= 1 Enable
= 0 Disable
Bit 2: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
Bit 1: Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
= 1 Enable
= 0 Disable
Bit 0: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
*Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing.
11.10 Logical Device 9 (GP I/O Port III)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP3 I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x00)
These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE] on 2-
byte boundary; they are available as you set GP32 to be an alternate function (General Purpose
Address Decode).
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Publication Release Date:April 1998
Revision 0.52