W83977ATF Datasheet, PDF (185/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
9.3.21 Bit Map Configuration Registers
Table 9-1: Bit Map of PM1 Register Block
Register Address
PM1STS1 <CR60, 61>
PM1STS2 <CR60,
61>+1H
PM1EN1 <CR60,
61>+2H
PM1EN2 <CR60,
61>+3H
PM1CTL1 <CR60,
61>+4H
PM1CTL2 <CR60,
61>+5H
PM1CTL3 <CR60,
61>+6H
PM1CTL4 <CR60,
61>+7H
PM1TMR1 <CR60,
61>+8H
PM1TMR2 <CR60,
61>+9H
PM1TMR3 <CR60,
61>+AH
PM1TMR4 <CR60,
61>+BH
Power-On
D7
D6
D5
D4
D3
D2
D1
Reset
Value
0000 0000
0
0
GBL_STS
BM_STS
0
0
0
0000 0000 WAK_STS
0
0
0
0
0
0
0000 0000
0
0
GBL_EN
0
0
0
0
0000 0000
0
0
0
0
0
0
0
0000 0000
0
0
0
0
0
GBL_RLS
BM_RLD
0000 0000
0
0
0
0
0
0
0
0000 0000
0
0
0
0
0
0
0
0000 0000
0
0
0
0
0
0
0
0000 0000 TMR_VAL7 TMR_VAL6 TMR_VAL5 TMR_VAL4 TMR_VAL3 TMR_VAL2 TMR_VAL1
0000 0000 TMR_VAL15 TMR_VAL14 TMR_VAL13 TMR_VAL12 TMR_VAL11 TMR_VAL10 TMR_VAL9
0000 0000 TMR_VAL23 TMR_VAL22 TMR_VAL21 TMR_VAL20 TMR_VAL19 TMR_VAL18 TMR_VAL17
0000 0000
0
0
0
0
0
0
D0
TMR_STS
0
TMR_EN
0
SCI_EN
0
0
0
TMR_VAL0
TMR_VAL8
TMR_VAL16
0
Table 9-2: Bit Map of GPE Register Block
Register Address Power-On D7
Reset Value
GP0STS1 <CR62, 63>
0000 0000
0
GP0STS2 <CR62,
63>+1H
0000 0000
0
GP0EN1 <CR62,
63>+2H
0000 0000
0
GP0EN2 <CR62,
63>+3H
0000 0000
0
GP1STS1 <CR64, 65>
0000 0000
0
GP1STS2 <CR64,
65>+1H
0000 0000
0
GP1EN1 <CR64,
65>+2H
0000 0000
0
GP1EN2 <CR64,
65>+3H
0000 0000
0
D6
D5
0
MOUSCISTS
0
0
0
MOUSCIEN
0
0
0
0
0
0
0
0
0
0
D4
KBCSCISTS
0
KBCSCIEN
0
0
0
0
0
D3
PRTSCISTS
0
PRTSCIEN
0
0
0
0
0
D2
FDCSCISTS
0
FDCSCIEN
0
0
0
0
0
D1
URASCISTS
0
URASCIEN
0
0
0
TMR_ON
BM_CNTRL
D0
URBSCISTS
0
URBSCIEN
0
BIOS_STS
0
BIOS_EN
BIOS_RLS
-129 -
Publication Release Date:April 1998
Revision 0.53