W83977ATF Datasheet, PDF (49/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
9.3.5 Power Management 1 Control Register 1 (PM1CTL1) .....................................................................119
9.3.6 Power Management 1 Control Register 2 (PM1CTL2) .....................................................................119
9.3.7 Power Management 1 Control Register 3 (PM1CTL3) .....................................................................120
9.3.8 Power Management 1 Control Register 4 (PM1CTL4) .....................................................................120
9.3.9 Power Management 1 Timer 1 (PM1TMR1).....................................................................................121
9.3.10 Power Management 1 Timer 2 (PM1TMR2) ...................................................................................121
9.3.11 Power Management 1 Timer 3 (PM1TMR3) ...................................................................................122
9.3.12 Power Management 1 Timer 4 (PM1TMR4) ...................................................................................123
9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1)..................................................................123
9.3.14 General Purpose Event 0 Status Register 2 (GP0STS2)..................................................................124
9.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1) .................................................................125
9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2) .................................................................125
9.3.17 General Purpose Event 1 Status Register 1 (GP1STS1)..................................................................126
9.3.18 General Purpose Event 1 Status Register 2 (GP1STS2)..................................................................126
9.3.19 General Purpose Event 1 Enable Register 1 (GP1EN1) .................................................................127
9.3.20 General Purpose Event 1 Enable Register 2 (GP1EN2) .................................................................127
9.3.21 Bit Map Configuration Registers ...................................................................................................129
10.0 SERIAL IRQ............................................................................................................130
10.1 START FRAME...................................................................................................................................131
10.2 IRQ/DATA FRAME ............................................................................................................................131
10.3 STOP FRAME .....................................................................................................................................132
10.4 RESET AND INITIALIZATION .........................................................................................................132
11.0 CONFIGURATION REGISTER............................................................................133
11.1 CHIP (GLOBAL) CONTROL REGISTER ...........................................................................................133
11.2 LOGICAL DEVICE 0 (FDC) ...............................................................................................................137
11.3 LOGICAL DEVICE 1 (PARALLEL PORT).........................................................................................140
11.4 LOGICAL DEVICE 2 (UART A)¢).....................................................................................................141
11.5 LOGICAL DEVICE 3 (UART B).........................................................................................................141
11.6 LOGICAL DEVICE 5 (KBC)...............................................................................................................142
11.7 LOGICAL DEVICE 6 (IR)...................................................................................................................143
11.8 LOGICAL DEVICE 7 (GP I/O PORT I)...............................................................................................144
11.9 LOGICAL DEVICE 8 (GP I/O PORT II) .............................................................................................148
11.10 LOGICAL DEVICE 9 (GP I/O PORT III) ..........................................................................................151
11.11 LOGICAL DEVICE A (ACPI) ...........................................................................................................154
Publication Release Date:April 1998
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Revision 0.52