W83977ATF Datasheet, PDF (62/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
TABLE 3-1 UART Register Bit Map
Bit Number
Register Address Base
0
1
2
3
4
+0
BDLAB = 0
Receiver
Buffer
Register
(Read Only)
RBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
+0
Transmitter TBR
BDLAB = 0 ^{Buffer Register}
(Write Only)
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
+1
Interrupt
ICR RBR Data
TBR
USR
HSR
0
BDLAB = 0
Control
Register
Ready
Interrupt
Empty
Interrupt
Interrupt
Enable
Interrupt
Enable
Enable
(ERDRI)
Enable
(ETBREI)
(EUSRI)
(EHSRI)
+2
Interrupt
ISR
"0" if
Interrupt
Interrupt
Interrupt
0
Status
Interrupt
Status
Status
Status
Register
(Read Only)
Pending
Bit (0)
Bit (1)
Bit (2)**
+2
UART FIFO UFR
FIFO
RCVR
Control
Enable
FIFO
Register
Reset
(Write Only)
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
+3
UART Control UCR
Data
Register
Length
Select
Bit 0
(DLS0)
Data
Length
Select
Bit 1
(DLS1)
Multiple
Stop Bits
Enable
(MSBE)
Parity
Bit
Enable
(PBE)
Even
Parity
Enable
(EPE)
+4
Handshake HCR
Data
Request Loopback
IRQ
Internal
Control
Terminal
to
RI
Enable
Loopback
Register
Ready
Send
Input
Enable
(DTR)
(RTS)
+5
UART Status USR RBR Data Overrun
Parity Bit
No Stop
Silent
Register
Ready
Error
Error
Bit
Byte
(RDR)
(OER)
(PBER)
Error
(NSER)
Detected
(SBD)
+6
Handshake HSR
CTS
DSR
RI Falling
DCD
Clear
Status Register
Toggling Toggling
Edge
Toggling
to Send
(TCTS)
(TDSR)
(FERI)
(TDCD)
(CTS)
+7
User Defined UDR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Register
+0
Baudrate
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
BDLAB = 1 ^{Divisor Latch}
Low
+1
Baudrate
BHL
Bit 8
BDLAB = 1 ^{Divisor Latch}
High
Bit 9
Bit 10
Bit 11
Bit 12
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
5
RX Data
Bit 5
TX Data
Bit 5
0
0
Reversed
Parity
Bit Fixed
Enable
PBFE)
0
TBR
Empty
(TBRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
6
RX Data
Bit 6
7
RX Data
Bit 7
TX Data
Bit 6
0
TX Data
Bit 7
0
FIFOs
Enabled
**
FIFOs
Enabled
**
RX
Interrupt
Active Level
(LSB)
RX
Interrupt
Active Level
(MSB)
Set
Silence
Enable
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
0
0
TSR
Empty
(TSRE)
Ring
Indicator
(RI)
Bit 6
RX FIFO
Error
Indication
(RFEI) **
Data Carrier
Detect
(DCD)
Bit 7
Bit 6
Bit 7
Bit 14
Bit 15
Publication Release Date: April 1998
-43 -
Revision 0.52