W83977ATF Datasheet, PDF (160/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
Bit 0: URBIRQEN.
= 0 disable the generation of an SMI interrupt due to UART B's IRQ.
= 1 enable the generation of an SMI interrupt due to UART B's IRQ.
CRF7 (Default 0x00)
Bit 7 - 2: Reserved. Return zero when read.
Bit 1: FSLEEP.
This bit selects the fast expiry time of individual devices.
= 0 1 second
= 1 8 milli-seconds
Bit 0: SMI_EN.
This bit is the SMI output pin enable bit. When an SMI event is raised on the output of the SMI
logic, setting this bit enables the SMI interrupt to be generated on the pin SMI . If this bit is
cleared, only the IRQ status bit in CRF3 is set and no SMI interrupt is generated on the pin SMI .
= 0 Disable SMI
= 1 Enable SMI
CRFE, FF (Default 0x00)
Reserved. Reserved for Winbond test.
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Publication Release Date:April 1998
Revision 0.52