W83977ATF Datasheet, PDF (172/207 Pages) Winbond – WINBOND I/O

W83977ATF
PRELIMINARY
The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A
register block may be a event register block which deals with ACPI events or a control register block
an enable register.
Each event register, if implemented, contains two registers: a status register and an enable register,
Interrupt ( SCI ). When the hardware event occurs, the corresponding status bit will be set. However,
the corresponding enable bit is also required to be set before an SCI
. If the
enable bit is not set, the software can examine the state of the hardware event by reading the status
SCI interrupt.
writing a 1 to its bit position,
status bit has a corresponding enable bit on the same bit position in the enable register. Those status
bits which have no corresponding enable bit are read for special purpose. Reversed or
The control bit in the control register provides some special control functions over hardware events,
or some special control over SCI event. Reserved or unimplemented control bits always return zero,
and writing to those bits should have no effect.
Table 9-1 lists the PM1 register block and the registers within it. The base address of PM1 register
block is named as PM1a_EVT_BLK in the ACPI specification and is specified in CR60, CR61 of
logical device A.
Table 9-2 lists the GPE register block and the register within it. The base address of general-purpose
event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in CR62, CR63
of logical device A. The base address of general-purpose event block GPE1 is named as GPE1_BLK
in the ACPI specification and is specified in CR64, CR65 of logical device A.
9.3.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
<CR60, 61> System I/O Space
Default Value:
00h
Attribute:
Read/write
Size:
8 bits
765
43
21
0
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
--
Publication Release Date:April 1998
Revision 0.53