W83977ATF Datasheet, PDF(192/207 Page) Winbond

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W83977ATF Datasheet, PDF (192/207 Pages) Winbond – WINBOND I/O

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W83977ATF

PRELIMINARY

The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write

operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the

trailing edge of IOW latches the data for the duration of the EPP write cycle.

PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address

read cycle to be performed and the data to be output to the host CPU.

5.2.5 EPP Data Port 0-3

These four registers are available only in EPP mode. Bit definitions of each data port are as follows:

76 5 4 3 2 1 0

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-

inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes

an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the

duration of the EPP write cycle.

During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read

cycle to be performed and the data to be output to the host CPU.

5.2.6 Bit Map of Parallel Port and EPP Registers

Data Port (R/W)

Status Buffer (Read)

PD7

BUSY

PD6 PD5

ACK PE

PD4

SLCT

Control Swapper (Read)

1 IRQEN

Control Latch (Write)

1 DIR IRQ

EPP Address Port R/W)

EPP Data Port 0 (R/W)

EPP Data Port 1 (R/W)

EPP Data Port 2 (R/W)

EPP Data Port 3 (R/W)

PD7

PD6 PD5 PD4

PD3

ERROR

SLIN

PD3

PD2

INIT

PD2

PD1

AUTOFD

PD1

PD0

TMOUT

STROBE

PD0

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Publication Release Date:April 1998

Revision 0.52

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