W968D6DA Datasheet, PDF (7/75 Pages) Winbond – Low-power features

W968D6DA
5. Pin Description
5.1 Signal Description
256Mb Async./Page,Syn./Burst CellularRAM
Symbol Type
Description
A[max:0]
Input
Address inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address
lines are also used to define the value to be loaded into the BCR or the RCR.
A[max:0] is A[23:0] for 256Mb.
CLK
(Note 1)
Input
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the
address is latched on the first rising CLK edge when ADV# is active. CLK is
static LOW during asynchronous access READ and WRITE operations and
during PAGE READ ACCESS operations.
ADV#
(Note 1)
CRE
CE#
Input
Input
Input
Address valid: Indicates that a valid address is present on the address inputs.
In asynchronous mode, addresses can be latched on the rising edge of ADV#
or ADV# can be held LOW. In synchronous mode, addresses are latched on the 1st rising
clock edge while ADV# is low. In synchronous mode, the ADV# low pulse width is 1 clock
cycle.
Control register enable: When CRE is HIGH, WRITE operations load the RCR
or BCR, and READ operations access the RCR, BCR, or DIDR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device
is disabled and goes into standby or deep power-down mode.
OE#
WE#
LB#
Input
Input
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is a WRITE to either a configuration register or to the memory array.
Lower byte enable. DQ[7:0] .
UB#
Input Upper byte enable. DQ[15:8] .
DQ[15:0] Input/Output Data inputs/outputs.
WAIT
(Note 1)
Output
Wait: Provides data-valid feedback during burst READ and WRITE
operations. The signal is gated by CE#. WAIT is used to arbitrate collisions
between refresh and READ/WRITE operations. WAIT is also asserted at the
end of a row unless wrapping within the burst length. WAIT is asserted and
should be ignored during asynchronous and page mode operations. WAIT is
High-Z when CE# is HIGH.
NC
—
No internal electrical connection is present.
VCC
Supply Device power supply: power supply for device core operation.
VCCQ
Supply I/O power supply: power supply for input/output buffers.
VSS
Supply VSS must be connected to ground.
VSSQ
Supply VSSQ must be connected to ground.
Note: 1. When using asynchronous mode or page mode exclusively, the CLK and ADV# inputs can be tied to VSS. WAIT will be
asserted but should be ignored during asynchronous and page mode operations.
Publication Release Date : June 27, 2013
-7-
Revision : A01-003