W968D6DA Datasheet, PDF (31/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8.4.3.12 Latency Counter (BCR[13:11])
Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation
and the first data value transferred. For allowable latency codes, see the following tables and figures.
8.4.3.13 Initial Access Latency (BCR[14])
Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT
must be monitored to detect delays caused by collisions with refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The
latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor
WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter.
8.4.3.14 Allowed Latency Counter Settings in Variable Latency Mode
BCR[13:11]
133 MHz Rated CRAM
010
Code 2: Max 66 MHz
011
Code 3: Max 104 MHz
100
Code 4: Max 133 MHz
Others
Reserved
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Publication Release Date : June 27, 2013
Revision : A01-003