W968D6DA Datasheet, PDF (54/75 Pages) Winbond – Low-power features

W968D6DA
10.2.13 Burst READ Row Boundary Crossing
CLK ^VIH
VIL
tCLK
A[max:0] ^VIH
VIL
256Mb Async./Page,Syn./Burst CellularRAM
ADV# ^VIH
VIL
LB#/UB#
VIH
VIL
CE#
VIH
VIL
OE#
VIH
VIL
WE# ^VIH
VIL
WAIT ^VOH
VOL
Note 2
DQ[15:0]
VOH
VOL
Valid
output
Valid
output
Valid
output
Valid
output
End of
row
Don‟t
Care
Note : 1. Non-default BCR settings for burst READ at end of row fixed or variable latency, WAIT active LOW, WAIT asserted
during delay (shown as solid line).
2.WAIT will be asserted for LC cycles for variable latency, or LC cycles for fixed latency.
- 54 -
Publication Release Date : June 27, 2013
Revision : A01-003