W968D6DA Datasheet, PDF (43/75 Pages) Winbond – Low-power features

W968D6DA
10.1.4 Burst WRITE Cycle Timing Requirements
Parameter
256Mb Async./Page,Syn./Burst CellularRAM
133MHz
Symbol
Min Man
104MHz
Min Max
Unit Notes
Address and ADV# LOW setup time
Address HOLD from ADV# HIGH (fixed
latency)
CE# HIGH between subsequent burst or
mixed-mode operations
Maximum CE# pulse width
tAS
0
tAVH 2
0
ns
1
2
ns
tCBPH 5
5
ns
2
tCEM
4
4
µs
2
CE# LOW to WAIT valid
Clock period
tCEW 1
7.5
1
7.5 ns
tCLK 7.5
9.62
ns
CE# setup to CLK active edge
tCSP 2.5
3
ns
Hold time from active CLK edge
tHD 1.5
2
ns
Chip disable to WAIT High-Z output
tHZ
7
8
ns
3
CLK rise or fall time
tKHKL
1.2
1.6 ns
Clock to WAIT valid
tKHTL
5.5
7
ns
CLK HIGH or LOW time
tKP
3
3
ns
Setup time to activate CLK edge
tSP
2
3
ns
Note: 1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
3. Low-Z to High-Z timings are tested with the AC Output Load circuit. The High-Z timings measure a 100mV transition
from either VOH or VOL toward VCCQ/2.
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Publication Release Date : June 27, 2013
Revision : A01-003