W968D6DA Datasheet, PDF (11/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8. FUNCTIONAL DESCRIPTION
In general, CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-
power, portable applications. The device implements the same high-speed bus interface found on burst mode Flash
products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode
accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
8.1 Power Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process.
Initialization will configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied
simultaneously. When they reach a stable level at or above 1.7V, the device will require 150μs to complete its self-
initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
8.1.1 Power-Up Initialization Timing
Vcc =1.7v
Vcc
VccQ
tpu _{> =150 us}
Device Initialization
Device ready for
normal operation
8.2 Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on flash products targeting low-power, wireless
applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The
specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh
configuration register (RCR[7]).
8.2.1 Asynchronous Modes
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry- standard SRAM
control bus (CE#, OE#, WE#, LB#/UB#). READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed.
WRITE operations occur when CE#, WE#, and LB#/UB# are driven LOW. During asynchronous WRITE operations,
the OE# level is a ―don't care,‖ and WE# will override OE#. The data to be written is latched on the rising edge of
CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the
ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is
enabled and its state should be ignored. WE# LOW time must be limited to tCEM.
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Publication Release Date : June 27, 2013
Revision : A01-003