W968D6DA Datasheet, PDF (65/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
10.2.24 Burst WRITE Interrupted by Burst WRITE or READ–Variable Latency Mode
CLK
V IH
V IL
A [ max : 0 ]
V IH
V IL
ADV #
V IH
V IL
tSP tHD
Valid
Address
tSP tHD
CE #
V IH
V IL
WE # ^{V IH}
V IL
tCSP
tSP tHD
WAIT
V OH
V OL
High - Z
OE # V IH
V ^{2 nd Cycle WRITE}
IL
tCLK
WRITE Burst interrupted with new WRITE or READ *2.
tSP tHD
Valid
Address
tSP tHD
tCEM*3
tSP tHD
tKHTL
tCEW
tSP tHD
tHD
High - Z
LB # / UB # ^{V IH}
V 2 nd Cycle WRITE
IL
DQ [ 15:0 ]IN ^{V IH}
V 2 nd Cycle WRITE IL
High - Z
tSP tHD
D0
OE# V IH
tSP tHD
D0 D1 D2 D3
tBOE
tOHZ
2nd Cycle READ V IL
tSP
tHD
LB#/UB# V IH
2nd Cycle READ V IL
tACLK tKOH
DQ[15:0] OUT V OH _{High - Z} V OH
2nd Cycle READ V OL
V OL
Vaild
Output
Vaild
Output
Vaild
Output
Vaild
Output
Don’t Care
Undefined
Note : 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable
latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency;
no refresh collision.
2. Burst interrupt shown on first allowable clock (i.e., after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
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Publication Release Date : June 27, 2013
Revision : A01-003