W968D6DA Datasheet, PDF (34/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8.4.3.19 Burst Write Always Produces Fixed Latency
For burst read, either variable or fixed latency mode is performed depending on BCR.bit14 value. For burst write,
only fixed latency mode is performed even if latency mode bit is configured in variable latency (BCR.bit14=0). The
fixed latency behavior of a write burst applies to burst initial access.
The controller has to observe maximum tCEM (= 4 µs) in case a write burst continues over long bursts. When CE#
being held low, no refresh operation can be scheduled properly, so that tCEM (= 4 µs) limitation applies.
8.4.3.20 Burst Interrupt
When any burst is complete or needs to be terminated to start new burst, bringing CE# high and back to low in next
clock cycle is highly recommended. Burst interrupt means an on-going burst is terminated by newly issued burst
initial command without toggling CE#. In this case, special care has to be taken to avoid any malfunction of
CellularRAM.
In any case, the burst interrupt is prohibited until the current burst initial command completes the first valid data cycle
(first data output or first data input cycle). At new burst initial command, DQ pins go into high-Z if ongoing burst is a
read. In case of write burst being interrupted, the data input is masked and will not be updated to the memory
location.
8.4.3.21 End-of-Row Condition
The CellularRAM in this design has the row size of 256-word , therefore the end of row condition takes place at every
address of FFH (FFH, 1FFH, 2FFH, ..). In continuous burst mode or wrap-off burst mode, if the burst operation
continues over the row boundary, the controller may not to terminate it by bringing CE high or interrupt it by starting a
new burst. To indicate the end of row condition, WAIT is asserted from the last data of previous row.
The end of row condition can also be detected (by controller) by tracking the address of ongoing burst, it is
available to read out the row size through accessing device ID register (DIDR).
8.4.3.22 Burst Termination or Burst Interrupt At the End of Row
T0
T1
T2
CLK
V IH
V IL
No later than 2
clocks after last data
CE #
V IH
V IL
CLK
V IH
V IL
CE #
V IH
V IL
T0
T1
T2
Low
V IH
ADV # _{V IL}
High
V IH
ADV # _{V IL}
2 clock cycles allowed for new Burst initial
WAIT
V OH
V OL
( WC = 1 ) ( WC = 0 )
DQ 0 ~ 15 ^{V OH}
V OL
Last data
DQ
Last - 1
DQ
last
WAIT
V OH
V OL
( WC = 1 ) ( WC = 0 )
DQ 0 ~ 15 ^{V OH}
V OL
DQ
Last - 1
Last data
DQ
last
[ Termination ]
[ Interrupt ]
8.4.3.23 Operating Mode (BCR[15])
Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
Note that when synchronous burst operation is programmed (BCR[15]=1), in addition to synchronous read/write,
asynchronous read/write operation is also allowed.
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Publication Release Date : June 27, 2013
Revision : A01-003