W968D6DA Datasheet, PDF (10/75 Pages) Winbond – Low-power features

W968D6DA
7. INSTRUCTION SET
7.1 Bus Operation
256Mb Async./Page,Syn./Burst CellularRAM
Asynchronous Mode
BCR [15]=1
Power
LB#/
CLK*1 ADV# CE# OE# WE# CRE
WAIT*2
UB#
DQ[15:0]*3
Note
Read
Active
L
L
L LHL
L Low-Z
Data out
4
Write
Active
L
L
LXL L
L Low-Z
Data in
4
Standby
Standby
L
X
HXX L
X High-Z
High-Z
5,6
No operation
Idle
L
X
L XX L
X Low-Z
X
4,6
Configuration register write
Active
L
L
L H L H X Low-Z
High-Z
Configuration register read
Active
L
L
L LHH
L Low-Z Config. reg. out
DPD
Deep power-down L
X
HXXX
X High-Z
High-Z
7
Burst Mode BCR [15]=0
Power
LB#/
CLK*1 ADV# CE# OE# WE# CRE
WAIT*2
UB#
DQ[15:0]*3
Note
Read
Active
L
L
L LHL
L Low-Z
Data out
4,8
Write
Active
L
L
LXL L
L Low-Z
Data in
4
Standby
Standby
L
X
HXX L
X High-Z
High-Z
5,6
No operation
Idle
L
X
L XX L
X Low-Z
X
4,6
Initial burst read
Active
L
L XH L
L Low-Z
X
4,9
Initial burst write
Active
L
LHL L
X Low-Z
X
4,9
Burst continue
Active
H
L XXX
L Low-Z Data in or Data out 4,9
Burst suspend
Active
X
X
L HXX
X Low-Z
High-Z
4,9
Configuration register write
Active
L
L H L H X Low-Z
High-Z
9,10
Configuration register read
Active
L
L LHH
L Low-Z Config. reg. out 9,10
DPD
Deep power-down L
X
HXXX
X High-Z
High-Z
7
Note: 1. CLK must be LOW during asynchronous read and asynchronous write modes; and to achieve standby power during standby and DPD
modes. CLK must be static (HIGH or LOW) during burst suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only
UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to
LOW.
8. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by all vendors. (Some vendors
also support asynchronous READ).
9. Burst mode operation is initialized through the bus configuration register (BCR[15]).
10. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as
indicated by WAIT).
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Publication Release Date : June 27, 2013
Revision : A01-003