W968D6DA Datasheet, PDF (42/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
10.1.3 Asynchronous WRITE Cycle Timing Requirements
Parameter
Symbol Min Max Unit Note
Address and ADV# LOW setup time
tAS
0
-
ns
Address HOLD from ADV# going HIGH
tAVH
2
-
ns
Address setup to ADV# going HIGH
tAVS
5
-
ns
Address valid to end of WRITE
tAW
70
-
ns
LB#/UB# select to end of WRITE
tBW
70
-
ns
CE# LOW to WAIT valid
tCEW
1
7.5 ns
CE# HIGH between subsequent asynchronous operations
tCPH
5
-
ns
CE# LOW to ADV# HIGH
tCVS
7
-
ns
Chip enable to end of WRITE
tCW
70
-
ns
Data HOLD from WRITE time
tDH
0
-
ns
Data WRITE setup time
tDW
20
-
ns
Chip disable to WAIT High-Z output
tHZ
-
8
ns
1
Chip enable to Low-Z output
tLZ
10
-
ns
2
End WRITE to Low-Z output
tOW
5
-
ns
2
ADV# pulse width
tVP
5
-
ns
ADV# setup to end of WRITE
tVS
70
-
ns
WRITE cycle time
tWC
70
-
ns
WRITE to DQ High-Z output
tWHZ
-
8
ns
1
WRITE pulse width
tWP
45
-
ns
3
WRITE pulse width HIGH
tWPH
10
-
ns
WRITE recovery time
tWR
0
-
ns
Note: 1. Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from
either VOH or VOL toward VCCQ/2.
2. High-Z to Low-Z timings are tested with AC Output Load Circuit. The Low-Z timings measure a 100mV transition away
from the High-Z (VCCQ/2) level toward either VOH or VOL.
3. WE# LOW time must be limited to tCEM (4μs).
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Publication Release Date : June 27, 2013
Revision : A01-003