W968D6DA Datasheet, PDF (4/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8.4.3.10 WAIT Configuration During Burst Operation ......................................................................................................... 30
8.4.3.11 WAIT Function by Configuration (WC) – Lat=2, WP=0 ......................................................................................... 30
8.4.3.12 Latency Counter (BCR[13:11]) .............................................................................................................................. 31
8.4.3.13 Initial Access Latency (BCR[14]) ........................................................................................................................... 31
8.4.3.14 Allowed Latency Counter Settings in Variable Latency Mode ............................................................................... 31
8.4.3.15 Latency Counter (Variable Initial Latency, No Refresh Collision) .......................................................................... 32
8.4.3.16 Latency Counter (Variable Initial Latency, With Refresh Collision) ....................................................................... 32
8.4.3.17 Allowed Latency Counter Settings in Fixed Latency Mode ................................................................................... 33
8.4.3.18 Latency Counter (Fixed Latency) .......................................................................................................................... 33
8.4.3.19 Burst Write Always Produces Fixed Latency......................................................................................................... 34
8.4.3.20 Burst Interrupt ....................................................................................................................................................... 34
8.4.3.21 End-of-Row Condition ........................................................................................................................................... 34
8.4.3.22 Burst Termination or Burst Interrupt At the End of Row ........................................................................................ 34
8.4.3.23 Operating Mode (BCR[15]).................................................................................................................................... 34
8.4.4 Refresh Configuration Register .................................................................................................................... 35
8.4.4.1 Refresh Configuration Register Mapping ................................................................................................................ 35
8.4.4.2 Partial Array Refresh (RCR[2:0] Default = Full Array Refresh ................................................................................. 35
8.4.4.3 Address Patterns for PAR (RCR[4] = 1) .................................................................................................................. 36
8.4.4.4 Deep Power-Down (RCR[4]) ................................................................................................................................... 36
8.4.4.5 Page Mode Operation (RCR[7]) .............................................................................................................................. 36
8.4.5 Device Identification Register ....................................................................................................................... 36
8.4.5.1 Device Identification Register Mapping ................................................................................................................... 36
8.4.6 Virtual Chip Enable Function: ....................................................................................................................... 36
9. ELECTRICAL CHARACTERISTIC ......................................................................................... 37
9.1 Absolute Maximum DC, AC Ratings .................................................................................................. 37
9.2 Electrical Characteristics and Operating Conditions .......................................................................... 38
9.3 Deep Power-Down Specifications......................................................................................................39
9.4 Partial Array Self Refresh Standby Current ....................................................................................... 39
9.5 Capacitance ....................................................................................................................................... 39
9.6 AC Input-Output Reference Waveform .............................................................................................. 39
9.7 AC Output Load Circuit ...................................................................................................................... 39
10. TIMING REQUIRMENTS ....................................................................................................... 40
10.1 Read, Write Timing Requirements ................................................................................................... 40
10.1.1 Asynchronous READ Cycle Timing Requirements..................................................................................... 40
10.1.2 Burst READ Cycle Timing Requirements ................................................................................................... 41
10.1.3 Asynchronous WRITE Cycle Timing Requirements ................................................................................... 42
10.1.4 Burst WRITE Cycle Timing Requirements.................................................................................................. 43
10.2 TIMING DIAGRAMS ........................................................................................................................ 44
10.2.1 Initialization Period ...................................................................................................................................... 44
10.2.2 DPD Entry and Exit Timing Parameters ..................................................................................................... 44
10.2.3 Initialization and DPD Timing Parameters .................................................................................................. 44
10.2.4 Asynchronous READ .................................................................................................................................. 45
10.2.5 Asynchronous READ Using ADV# ............................................................................................................. 46
10.2.6 Page Mode READ....................................................................................................................................... 47
10.2.7 Single-Access Burst READ Operation-Variable Latency............................................................................ 48
10.2.8 4-Word Burst READ Operation-Variable Latency....................................................................................... 49
10.2.9 Single-Access Burst READ Operation-Fixed Latency ................................................................................ 50
10.2.10 4-Word Burst READ Operation-Fixed Latency ......................................................................................... 51
10.2.11 READ Burst Suspend ............................................................................................................................... 52
10.2.12 Burst READ at End-of-Row (Wrap Off)..................................................................................................... 53
10.2.13 Burst READ Row Boundary Crossing....................................................................................................... 54
10.2.14 CE#-Controlled Asynchronous WRITE..................................................................................................... 55
10.2.15 LB# / UB# Controlled Asynchronous WRITE............................................................................................ 56
10.2.16 WE# - Controlled Asynchronous WRITE .................................................................................................. 57
10.2.17 Asynchronous WRITE Using ADV# .......................................................................................................... 58
10.2.18 Burst WRITE Operation-Variable Latency Mode ...................................................................................... 59
10.2.19 Burst WRITE Operation-Fixed Latency Mode .......................................................................................... 60
Publication Release Date : June 27, 2013
-4-
Revision : A01-003