W968D6DA Datasheet, PDF (64/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
10.2.23 Burst READ Interrupted by Burst READ or WRITE
CLK
V IH
V IL
A [ max : 0 ]
V IH
V IL
ADV
#
V IH
V IL
CE #
V IH
V IL
WE # ^{V IH}
V IL
WAIT
V
V
OH
OL
OE # V IH
V ^{2 nd Cycle READ} IL
LB # / UB # ^{V IH}
V 2 nd Cycle READ IL
DQ [ 15:0 ] ^{V OH}
V 2 nd Cycle READ OL
tCLK
READ Burst interrupted with new READ or WRITE. *2
tSP tHD
Valid
Address
tSP tHD
tSP _tHD
Valid
Address
tSP tHD
tCSP
tSP _tHD
tCEM*3
tSP tHD
tBOE
tKHTL _tBOE
tCEW ^tOHZ
tHD
High - Z
tOHZ
tACLK ^tKOH
tBOE
High - Z
Valid
Output
High - Z
OE# V IH
Valid
Output
Valid
Valid
Output Output
tACLK
Valid
Output
2 nd Cycle WRITE _{V IL}
LB#/UB# V IH
2 nd Cycle WRITE V IL
tSP tHD
DQ[15:0]IN V IH
2 nd Cycle WRITE V IL ^High-Z
D0 D1 D2 D3
Don‟t Care
Undefined
Note : 1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code 2(3
clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
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Publication Release Date : June 27, 2013
Revision : A01-003